In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have bee...In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.展开更多
Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （...Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （SEU） cross sections under tilted ion strikes are overestimated by 23.9%-84.6%, compared with under normally incident ion with the equivalent linear energy transfer （LET） value of 41 MeV/（mg/cm2）, which can be partially explained by the fact that the MBU rate for tilted ions of 30° is 8.5%-9.8% higher than for normally incident ions. While at a lower LET of - 9.5 MeV/（mg/cm2）, no clear discrepancy is observed. Moreover, since the ion trajectories at normal and tilted incidences are different, the predominant double-bit upset （DBU） patterns measured are different in both conditions. Those differences depend on the LET values of heavy ions and devices under test. Thus, effective LET method should be used carefully in ground-based testing of single event effects （SEE） sensitivity, especially in MBU-sensitive devices.展开更多
基于Synopsys公司3D TCAD器件模拟,该文通过改变3种工艺参数,研究65 nm体硅CMOS工艺下PMOS晶体管工艺参数变化对静态随机存储器(Static Random Access Memory,SRAM)存储单元翻转恢复效应的影响。研究结果表明:降低PMOS晶体管的P+深阱掺...基于Synopsys公司3D TCAD器件模拟,该文通过改变3种工艺参数,研究65 nm体硅CMOS工艺下PMOS晶体管工艺参数变化对静态随机存储器(Static Random Access Memory,SRAM)存储单元翻转恢复效应的影响。研究结果表明:降低PMOS晶体管的P+深阱掺杂浓度、N阱掺杂浓度或调阈掺杂浓度,有助于减小翻转恢复所需的线性能量传输值(Linear Energy Transfer,LET);通过降低PMOS晶体管的P+深阱掺杂浓度和N阱掺杂浓度,使翻转恢复时间变长。该文研究结论有助于优化SRAM存储单元抗单粒子效应(Single-Event Effect,SEE)设计,并且可以指导体硅CMOS工艺下抗辐射集成电路的研究。展开更多
基金supported by the National Natural Science Foundation of China (Grant No. 11175138)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20100201110018)the Key Program of the National Natural Science Foundation of China (Grant No. 11235008)
文摘In this work single event upset(SEU) sensitivity of 45 nm fully depleted silicon-on-insulator(FDSOI) static random access memory(SRAM) cell and that of SOI fin-shaped field-effect-transistor(FinFET) SRAM cell have been investigated by 3D TCAD simulations.The critical charges and SEU threshold linear energy transfer(LET) value of the two SRAM cells are consistent due to similar gate capacitance.The low electrical field and the high recombination rate account for the non-sensitivity to SEU in heavily doped drain region.Compared with FDSOI SRAM,SOI FinFET SRAM cell exhibits lower SEU sensitivity at the center of the gate.The smaller sensitive area in SOI FinFET SRAM cell may result in a smaller SEU saturation cross section than that of SOI FinFET SRAM.
基金supported by the National Natural Science Foundation of China(Grant Nos.11179003,10975164,10805062,and 11005134)
文摘Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （SEU） cross sections under tilted ion strikes are overestimated by 23.9%-84.6%, compared with under normally incident ion with the equivalent linear energy transfer （LET） value of 41 MeV/（mg/cm2）, which can be partially explained by the fact that the MBU rate for tilted ions of 30° is 8.5%-9.8% higher than for normally incident ions. While at a lower LET of - 9.5 MeV/（mg/cm2）, no clear discrepancy is observed. Moreover, since the ion trajectories at normal and tilted incidences are different, the predominant double-bit upset （DBU） patterns measured are different in both conditions. Those differences depend on the LET values of heavy ions and devices under test. Thus, effective LET method should be used carefully in ground-based testing of single event effects （SEE） sensitivity, especially in MBU-sensitive devices.
文摘基于Synopsys公司3D TCAD器件模拟,该文通过改变3种工艺参数,研究65 nm体硅CMOS工艺下PMOS晶体管工艺参数变化对静态随机存储器(Static Random Access Memory,SRAM)存储单元翻转恢复效应的影响。研究结果表明:降低PMOS晶体管的P+深阱掺杂浓度、N阱掺杂浓度或调阈掺杂浓度,有助于减小翻转恢复所需的线性能量传输值(Linear Energy Transfer,LET);通过降低PMOS晶体管的P+深阱掺杂浓度和N阱掺杂浓度,使翻转恢复时间变长。该文研究结论有助于优化SRAM存储单元抗单粒子效应(Single-Event Effect,SEE)设计,并且可以指导体硅CMOS工艺下抗辐射集成电路的研究。
