Time-delay Correction Control Strategy for HVDC Frequency Regulation Services

With the advancements in voltage source converter(VSC)technology,VSC based high voltage direct current(VSCHVDC)systems provide system operators with a prospective approach to enhance system operating stability and resilience.In addition to long-distance transmission,the VSC-HVDC system can also provide multiple ancillary services,such as frequency regulation,due to its power controllability.However,if a time delay exists in the control signal,the VSC-HVDC system may bring destabilizing influences to the system,which will decrease the system resilience under the disturbance.In order to reduce control deviation caused by time delay,in this paper,a small signal model is first conducted to analyze the impact of time delay on system stability.Then a time-delay correction control strategy for HVDC frequency regulation control is developed to reduce the influence of the time delay.The control performance of the proposed time-delay correction control is verified both in the established small signal model and the runtime simulation in a modified IEEE 39 bus system.The results indicate that the proposed time-delay correction control strategy shows significant improvement in system stability.

A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect

In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi- tion to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static （NQS） small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD sim- ulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgal and Cgd2, the intrinsic front and back distributed channel resistance, Rgdl and Rgd2 respectively, the transport de- lay, rm, and the inductance, Lsd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.