In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi- tio...In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi- tion to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static （NQS） small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD sim- ulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgal and Cgd2, the intrinsic front and back distributed channel resistance, Rgdl and Rgd2 respectively, the transport de- lay, rm, and the inductance, Lsd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.展开更多
文摘In analog circuit design an important parameter, from the perspective of superior device performance, is linearity. The DG MOSFET in asymmetric mode operation has been found to present a better linearity. In addi- tion to that it provides, at the discretion of analog circuit designer, an additional degree of freedom, by providing independent bias control for the front and the back gates. Here a non-quasi-static （NQS） small signal model for DGMOSFET with asymmetric gate bias is proposed for extracting the parameters of the device using TCAD sim- ulations. The parameters extracted here for analysis are the intrinsic front and back gate to drain capacitance, Cgal and Cgd2, the intrinsic front and back distributed channel resistance, Rgdl and Rgd2 respectively, the transport de- lay, rm, and the inductance, Lsd. The parameter extraction model for an asymmetric DG MOSFET is validated with pre-established extracted parameter data, for symmetric DG MOSFET devices, from the available literature. The device simulation is performed with respect to frequency up to 100 GHz.
