Single event effects evaluation on convolution neural network in Xilinx 28 nm system on chip

Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.

System-on-a-Chip (SoC) Based Hardware Acceleration for Video Codec

Nowadays, from home monitoring to large airport security, a lot of digital video surveillance systems have been used. Digital surveillance system usually requires streaming video processing abilities. As an advanced video coding method, H.264 is introduced to reduce the large video data dramatically (usually by 70X or more). However, computational overhead occurs when coding and decoding H.264 video. In this paper, a System-on-a-Chip (SoC) based hardware acceleration solution for video codec is proposed, which can also be used for other software applications. The characteristics of the video codec are analyzed by using the profiling tool. The Hadamard function, which is the bottleneck of H.264, is identified not only by execution time but also another two attributes, such as cycle per loop and loop round. The Co-processor approach is applied to accelerate the Hadamard function by transforming it to hardware. Performance improvement, resource costs and energy consumption are compared and analyzed. Experimental results indicate that 76.5% energy deduction and 8.09X speedup can be reached after balancing these three key factors.

单片集成计算机系统SOC(System—On—Chip)应用探讨

介绍了目前国际上新发展的单片集成计算机系统SOC(System—On—Chip),按照不同的用途,选取不同功能模块的芯片,只需要很少的外部器件就可以完成普通PC所具有的常用功能,功能比以往的微处理器要强大得多,它的内部属于PC的构架,可扩展性强,同时使产品具有体积小巧、成本低廉的优势。

基于SABO-GRU-Attention的锂电池SOC估计

提出一种基于SABO-GRU-Attention(subtraction average based optimizer-gate recurrent unitattention)的锂电池SOC(state of charge)估计方法。采用基于平均减法优化算法自适应更新GRU神经网络的超参数,融合SE(squeeze and excitation)注意力机制自适应分配各通道权重,提高学习效率。对马里兰大学电池数据集进行预处理,输入电压、电流参数,进行锂电池充放电仿真实验,并搭建锂电池荷电状态实验平台进行储能锂电池充放电实验。结果表明,提出的SOC神经网络估计模型明显优于LSTM、GRU以及PSO-GRU等模型,具有较高的估计精度与应用价值。

Optimization of Multiplex PCR Systems for Gene-chip Detection of Mutations in Exons in cTnI Gene Associated with FHCM

Hypertrophic cardiomyopathy (HCM) is one of the diseases damaging people health most badly and some mutations of exons in cardiac troponin I (cTnI) gene are closely associated with family hypertrophic cardiomyopathy (FHCM).A microarray was fabricated to screen mutations in exons 3,5,7,and 8 in cTnI gene.Primers were designed for the PCR (polymerase chain reaction) to amplify the target DNA fragments from fresh blood samples.In order to simplify the PCR process,multiplex PCR technology was investigated in detail.The concentration of Mg^(2+) played an important role in multiplex PCR process,a properly low concentration of Mg^(2+) submitted a better speciality of PCR products.The speciality was also favored when the annealing temperature was reasonably enhanced and 64℃is the optimal annealing temperature for the multiplex PCR systems.When applying the fabricated gene-chip to detect the target fragments from PCR mixture,the signal intensity sequence is in accordance with that from theoretic estimate.

Effect of Implanted Chip System on Blood Pressure Regulation in Rabbits

Objective: To evaluate the efficiency of an implanted chip system on blood pressure regulation. Methods: The mean arterial pressure (MAP) and heart rate (HR) were recorded in anesthetized rabbits. Based on the set point theory, an implanted chip system was designed to regulate the blood pressure by stimulating the aortic depressor nerve (ADN) according to the feedback of blood pressure. The blood pressure regulation induced by the implanted chip system was carried out twice (lasted for 15 min and 60 min respectively) and the change of MAP and HR during the regulation was compared with the control. Results: There was a significant decrease of MAP during the first regulation ([-32.0 ± 6.6] mmHg) and second regulation ([-27.4 ± 6.2] mmHg) compared with the control (P<0.01). The HR was also significantly decreased during regulation compared with the control. Both MAP and HR returned to the baseline immediately without rebound after the regulation ceased. Conclusion: The implanted chip system can regulate the blood pressure successfully and keep the blood pressure in a lower constant level without adaptation.

片上系统（SoC：System—on-a—chip）

片上系统指的是在单个芯片上集成一个完整的系统，对所有或部分必要的电子电路进行包分组的技术。所谓完整的系统一般包括中央处理器（CPU）、存储器、以及外围电路等。SoC是与其它技术并行发展的，如绝缘硅（SOI），它可以提供增强的时钟频率，从而降低微芯片的功耗。

Straw return increases crop production by improving soil organic carbon sequestration and soil aggregation in a long-term wheat-cotton cropping system

Straw return is a promising strategy for managing soil organic carbon(SOC)and improving yield stability.However,the optimal straw return strategy for sustainable crop production in the wheat(Triticum aestivum L.)-cotton(Gossypium hirsutum L.)cropping system remains uncertain.The objective of this study was to quantify the long-term(10 years)impact of carbon(C)input on SOC sequestration,soil aggregation and crop yields in a wheat-cotton cropping system in the Yangtze River Valley,China.Five treatments were arranged with a single-factor randomized design as follows:no straw return(Control),return of wheat straw only(Wt),return of cotton straw only(Ct),return of 50%wheat and 50%cotton straw(Wh-Ch)and return of 100%wheat and 100%cotton straw(Wt-Ct).In comparison to the Control,the SOC content increased by 8.4 to 20.2%under straw return.A significant linear positive correlation between SOC sequestration and C input(1.42-7.19 Mg ha^(−1)yr^(−1))(P<0.05)was detected.The percentages of aggregates of sizes>2 and 1-2 mm at the 0-20 cm soil depth were also significantly elevated under straw return,with the greatest increase of the aggregate stability in the Wt-Ct treatment(28.1%).The average wheat yields increased by 12.4-36.0%and cotton yields increased by 29.4-73.7%,and significantly linear positive correlations were also detected between C input and the yields of wheat and cotton.The average sustainable yield index(SYI)reached a maximum value of 0.69 when the C input was 7.08 Mg ha^(−1)yr^(−1),which was close to the maximum value(SYI of 0.69,C input of 7.19 Mg ha^(−1)yr^(-1))in the Wt-Ct treatment.Overall,the return of both wheat and cotton straw was the best strategy for improving SOC sequestration,soil aggregation,yields and their sustainability in the wheat-cotton rotation system.

Efficient stochastic parallel gradient descent training for on-chip optical processor

In recent years,space-division multiplexing(SDM)technology,which involves transmitting data information on multiple parallel channels for efficient capacity scaling,has been widely used in fiber and free-space optical communication sys-tems.To enable flexible data management and cope with the mixing between different channels,the integrated reconfig-urable optical processor is used for optical switching and mitigating the channel crosstalk.However,efficient online train-ing becomes intricate and challenging,particularly when dealing with a significant number of channels.Here we use the stochastic parallel gradient descent(SPGD)algorithm to configure the integrated optical processor,which has less com-putation than the traditional gradient descent(GD)algorithm.We design and fabricate a 6×6 on-chip optical processor on silicon platform to implement optical switching and descrambling assisted by the online training with the SPDG algorithm.Moreover,we apply the on-chip processor configured by the SPGD algorithm to optical communications for optical switching and efficiently mitigating the channel crosstalk in SDM systems.In comparison with the traditional GD al-gorithm,it is found that the SPGD algorithm features better performance especially when the scale of matrix is large,which means it has the potential to optimize large-scale optical matrix computation acceleration chips.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

An Implanted Closed-loop Chip System for Heart Rate Control:System Design and Effects in Conscious Rats

Objective： To evaluate the efficiency of an implanted chip system for the control of heart rate （HR）. Methods： The HR was recorded in six conscious Sprague-Dawley （SD） rats. An implanted chip system was designed to regulate the HR by stimulating the right cervical vagus nerve according to the feedback of real time HR. Each rat was subjected to 30-min regulation and 30-min recovery. The change of HR during the regulation period was compared with the control. The ECG was recorded during the experiment for 24 h. Results： The ECG signals were successfully recorded during the experiment. The HR was significantly decreased during the period of regulation compared with control （-79.3 ± 34.5, P 〈 0.01, n = 6） and then recovered to normal after regulation. Conclusion： The described implanted chip system can regulate the HR to a designated set point.

基于Python脚本的SoC寄存器模块自动化设计

片上系统芯片(SoC)包含大量可通过系统总线配置的寄存器模块。在芯片设计流程中,需要人工设计寄存器模块功能,并形成可阅读的设计文档,再由硬件描述语言(Hardware Description Language)描述为实际数字电路,还需要有便于芯片仿真验证的寄存器模型以及基于C语言的嵌入式固件程序用于应用软件开发。本文提供一种基于Python脚本语言的芯片设计流程,将上述芯片设计流程串联起来,做到一次规格设计,自动化输出寄存器模块的不同设计描述,有效提高了SoC芯片设计效率。

Simulation and fabrication of in vitro microfluidic microelectrode array chip for patterned culture and electrophysiological detection of neurons

To enable the detection and modulation of modularized neural networks in vitro,this study proposes a microfluidic microelectrode array chip for the cultivation,compartmentalization,and control of neural cells.The chip was designed based on the specific structure of neurons and the requirements for detection and modulation.Finite-element analysis of the chip’s flow field was conducted using the COMSOL Multiphysics software,and the simulation results show that the liquid within the chip can flow smoothly,ensuring stable flow fields that facilitate the uniform growth of neurons within the microfluidic channels.By employing MEMS technology in combination with nanomaterial modification techniques,the microfluidic microelectrode array chip was fabricated successfully.Primary hippocampal neurons were cultured on the chip,forming a well-defined neural network.Spontaneous electrical activity of the detected neurons was recorded,exhibiting a 23.7%increase in amplitude compared to neuronal discharges detected on an open-field microelectrode array.This study provides a platform for the precise detection and modulation of patterned neuronal growth in vitro,potentially serving as a novel tool in neuroscience research.

Single-event-effect propagation investigation on nanoscale system on chip by applying heavy-ion microbeam and event tree analysis

The propagation of single-event effects(SEEs)on a Xilinx Zynq-7000 system on chip(SoC)was inves-tigated using heavy-ion microbeam radiation.The irradia-tion results reveal several functional blocks’sensitivity locations and cross sections,for instance,the arithmetic logic unit,register,D-cache,and peripheral,while irradi-ating the on-chip memory(OCM)region.Moreover,event tree analysis was executed based on the obtained microbeam irradiation results.This study quantitatively assesses the probabilities of SEE propagation from the OCM to other blocks in the SoC.

The Application of Multitasking Mechanism in Single Chip Computer System

Developed a new program structure using in single chip computer system, which based on multitasking mechanism. Discussed the specific method for realization of the new structure. The applied sample is also provided.

On-chip quantum NOON state sensing for temperature and humidity

A maximal photon number entangled state,namely NOON state,can be adopted for sensing with a quantum enhancedprecision.In this work,we designed silicon quantum photonic chips containing two types of Mach-Zehnder interferometerswherein the two-photon NOON state,sensing element for temperature or humidity,is generated.Compared with classicallight or single photon case,two-photon NOON state sensing shows a solid enhancement in the sensing resolution andprecision.As the first demonstration of on-chip quantum photonic sensing,it reveals the advantages of photonic chips forhigh integration density,small-size,stability for multiple-parameter sensing serviceability.A higher sensing precision isexpected to beat the standard quantum limit with a higher photon number NOON state.

Use of single chip microcomputer in hydraulic digital adaptive control system

Presents a one grade adaptive controller with one reference model which is built according to δ MRACS adaptive control theory and used to control an actual high order hydraulic system, and the whole hardware system used, which includes a AT89C51 single chip microcomputer, 74Ls373 flip latch, 6116 store, eight bit ADC0809, and so on, and the satisfactory results obtained in study on hydraulic control system.

基于System-on-Chip技术的超高速遥测系统的实现

文章阐述了基于片上系统(System-on-Chip)技术的超高速CCSDS(空间数据系统咨询委员会:ConsultativeCommittee on Space Data Systems)遥测系统的实现。该系统用于支持CCSDS和非CCSDS的常规飞行器,同时也是遥感地面站的一个重要部分。本文着重于讨论采用高速现场可编程器件(FPGA)实现的遥测数据处理系统,包括容错帧同步、帧同步保护、解扰和RS解码、SoC。

Simplified quantitative analysis method and its application in the insitu synthesized copper-based azide chips

Copper-based azide(Cu(N_(3))2 or CuN_(3),CA)chips synthesized by in-situ azide reaction and utilized in miniaturized explosive systems has become a hot research topic in recent years.However,the advantages of in-situ synthesis method,including small size and low dosage,bring about difficulties in quantitative analysis and differences in ignition capabilities of CA chips.The aim of present work is to develop a simplified quantitative analysis method for accurate and safe analysis of components in CA chips to evaluate and investigate the corresponding ignition ability.In this work,Cu(N_(3))2 and CuN_(3)components in CA chips were separated through dissolution and distillation by utilizing the difference in solubility and corresponding content was obtained by measuring N_(3)-concentration through spectrophotometry.The spectrophotometry method was optimized by studying influencing factors and the recovery rate of different separation methods was studied,ensuring the accuracy and reproducibility of test results.The optimized method is linear in range from 1.0-25.0 mg/L,with a correlation coefficient R^(2)=0.9998,which meets the requirements of CA chips with a milligram-level content test.Compared with the existing ICP method,component analysis results of CA chips obtained by spectrophotometry are closer to real component content in samples and have satisfactory accuracy.Moreover,as its application in miniaturized explosive systems,the ignition ability of CA chips with different component contents for direct ink writing CL-20 and the corresponding mechanism was studied.This study provided a basis and idea for the design and performance evaluation of CA chips in miniaturized explosive systems.

A novel integrated microfluidic chip for on-demand electrostatic droplet charging and sorting

On-demand droplet sorting is extensively applied for the efficient manipulation and genome-wide analysis of individual cells.However,state-of-the-art microfluidic chips for droplet sorting still suffer from low sorting speeds,sample loss,and labor-intensive preparation procedures.Here,we demonstrate the development of a novel microfluidic chip that integrates droplet generation,on-demand electrostatic droplet charging,and high-throughput sorting.The charging electrode is a copper wire buried above the nozzle of the microchannel,and the deflecting electrode is the phosphate buffered saline in the microchannel,which greatly simplifies the structure and fabrication process of the chip.Moreover,this chip is capable of high-frequency droplet generation and sorting,with a frequency of 11.757 kHz in the drop state.The chip completes the selective charging process via electrostatic induction during droplet generation.On-demand charged microdroplets can arbitrarilymove to specific exit channels in a three-dimensional(3D)-deflected electric field,which can be controlled according to user requirements,and the flux of droplet deflection is thereby significantly enhanced.Furthermore,a lossless modification strategy is presented to improve the accuracy of droplet deflection or harvest rate from 97.49% to 99.38% by monitoring the frequency of droplet generation in real time and feeding it back to the charging signal.This chip has great potential for quantitative processing and analysis of single cells for elucidating cell-to-cell variations.