A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can ...A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.展开更多
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a （n, n-1, m, 3） convolutional code is presented. When the proposed theorems ar...This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a （n, n-1, m, 3） convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit （X bit）. When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.展开更多
基金supported by the 44th China Postdoctoral Science Foundation funded project
文摘A novel built-in self-test （BIST） approach to test the configurable input/output buffers in Xilinx Virtex series SoCs （system on a chip） using hard macro has been proposed in this paper. The proposed approach can completely detect single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs （field programmable gate configurations are required array）. Only total of 10 to completely test the I/O buffers of Virtex devices.
基金supported in part by the National Basic Research Program of China(973)(Grant Nos.2005CB321604 and 2005CB321605)in part by the National Natural Science Foundation of China(Grant Nos.90207002 and 60576031).
文摘This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a （n, n-1, m, 3） convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit （X bit）. When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.
