Reducing vulnerability to soft errors in sub-100 nm content addressable memory circuits

We first study the impacts of soft errors on various types of CAM for different feature sizes.After presenting a soft error immune CAM cell,SSB-RCAM,we propose two kinds of reliable CAM,DCF-RCAM and DCK-RCAM. In addition,we present an ignore mechanism to protect dual cell redundancy CAMs against soft errors.Experimental results indicate that the 11T-NOR CAM cell has an advantage in soft error immunity.Based on 11T-NOR,the proposed reliable CAMs reduce the SER by about 81%on average with acceptable overheads.The SER of dual cell redundancy CAMs can also be decreased using the ignore mechanism in specific applications.

Prevention from Soft Errors via Architecture Elasticity

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.

SS-SERA:An improved framework for architectural level soft error reliability analysis

Integrated with an improved architectural vulnerability factor （AVF） computing model, a new architectural level soft error reliability analysis framework, SS-SERA （soft error reliability analysis based on SimpleScalar）, was developed. SS-SERA was used to estimate the AVFs for various on-chip structures accurately. Experimental results show that the AVFs of issue queue （IQ）, register update units （RUU）, load store queue （LSQ） and functional unit （FU） are 38.11%, 22.17%, 23.05% and 24.43%, respectively. For address-based structures, i.e., levell data cache （LID）, DTLB, level2 unified cache （L2U）, levell instruction cache （LII） and ITLB, AVFs of their data arrays are 22.86%, 27.57%, 14.80%, 8.25% and 12.58%, lower than their tag arrays＇ AVFs which are 30.01%, 28.89%, 17.69%, 10.26% and 13.84%, respectively. Furthermore, using the AVF values obtained with SS-SERA, a qualitative and quantitative analysis of the AVF variation and predictability was performed for the structures studied. Experimental results show that the AVF exhibits significant variations across different structures and workloads, and is influenced by multiple microarchitectural metrics and their interactions. Besides, AVFs of SPEC2K floating point programs exhibit better predictability than SPEC2K integer programs.

STUDY ON A NEW TYPE OF THROW-AWAY SOFT GRINDING WHEELS

In accordance with the difficult problems of belt cross vibrations and effects of belt tension on machine spindle precision in abrasive belt grinding, a new soft grinding wheel is put forward, which is provided with the advantages of belt grinding and can he installed directly on the grinding machine spindle substituting for common grinding wheels. The new soft grinding wheel does not need any ancillary facilities and dressing devices in banding. With analyzing error of wheel and grinding experiment, the high-efficiency grinding characteristics grinding hard-brittle materials has been obtained.

A novel double-node-upset-resilient radiation-hardened latch

To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology.Using three interlocked single-node-upset-resilient cells,which are identically mainly constructed from three mutually feeding back 2-input C-elements,the latch achieves double-node-upset-resilience.Using smaller transistor sizes,clock-gating technology,and high-speed transmission-path,the cost of the latch is effectively reduced.Simulation results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches,the proposed latch reduces the transmission delay by 72.54%,the power dissipation by 33.97%,and the delay-power-area product by 78.57%,while the average cost of the silicon area is only increased by 16.45%.

Direct measurement of an energy-dependent single-event-upset cross-section with time-of-flight method at CSNS

To predict the soft error rate for applications, it is essential to study the energy dependence of the single-event-upset(SEU) cross-section. In this work, we present a direct measurement of the SEU cross-section with the Back-n white neutron source at the China Spallation Neutron Source. The measured cross section is consistent with the soft error data from the manufacturer and the result suggests that the threshold energy of the SEU is about 0.5 Me V, which confirms the statement in Iwashita’s report that the threshold energy for neutron soft error is much below that of the(n, α) cross-section of silicon.In addition, an index of the effective neutron energy is suggested to characterize the similarity between a spallation neutron beam and the standard atmospheric neutron environment.

ON THE EQUIVALENCE OF PDA ALGORITHM AND SIC-MMSE ALGORITHM

In this letter,by employing Gaussian distribution to approximate the probability density function(pdf) of the extrinsic information at the output of the multiuser detector as a function of the pdf of the input extrinsic messages,it is concluded that the Probabilistic Data Association(PDA) algorithm is equivalent to the Soft Interference Cancellation plus Minimum Mean Square Error algo-rithm(SIC-MMSE) .

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

Mechanisms of atmospheric neutron-induced single event upsets in nanometric SOI and bulk SRAM devices based on experiment-verified simulation tool

In this paper, a simulation tool named the neutron-induced single event effect predictive platform（NSEEP^2） is proposed to reveal the mechanism of atmospheric neutron-induced single event effect（SEE） in an electronic device, based on heavy-ion data and Monte-Carlo neutron transport simulation. The detailed metallization architecture and sensitive volume topology of a nanometric static random access memory（SRAM） device can be considered to calculate the real-time soft error rate（RTSER） in the applied environment accurately. The validity of this tool is verified by real-time experimental results. In addition, based on the NSEEP^2, RTSERs of 90 nm–32 nm silicon on insulator（SOI） and bulk SRAM device under various ambient conditions are predicted and analyzed to evaluate the neutron SEE sensitivity and reveal the underlying mechanism. It is found that as the feature size shrinks, the change trends of neutron SEE sensitivity of bulk and SOI technologies are opposite, which can be attributed to the different MBU performances. The RTSER of bulk technology is always 2.8–64 times higher than that of SOI technology, depending on the technology node, solar activity, and flight height.

Multi-objective Particle Swarm Optimization Algorithm Based on Performance and Reliability of Discrete System Resources Configuration

Considering research on multi-objective optimization for reliability and performance suffering cost constraints in digital circuits,an improved multi-objective optimization algorithm based on performance and reliability was proposed to solve the problem of discrete system resources configuration in this paper. This algorithm used the particle-swarm optimization( PSO) to evaluate the tradeoffs configuration of the system resources between reliability and performance and proved the feasibility through the simulation.Finally, the information of resources configuration from optimization algorithm was used to effectively guide the system design so as to mitigate soft errors caused by single event effect( SEE).

A Fault-Tolerant FPGA Architecture

SRAM （Static RAM）-based FPGAs （Field Programmable Gate Arrays （FPGAs） have gained wide acceptance due to their on-line reconfigurable features. The growing demand for FPGAs has motivated semiconductor chip manufacturers to build more densely packed FPGAs with higher logic capacity. The downside of high density devices is that the probability of errors in such devices tends to increase. This paper proposes an FPGA architecture that is composed of an array of cells with built in error correction capability. Collectively a group of such cells can implement any logic function that is either registered or combinational. A cell is composed of three units： a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell. The director block can transmit output data from the logic block to another cell located at its South, North, East or West, or to cells in all four directions. Thus a functional cell can also be used to route signals to other functional cells, thus avoiding any intricate network of interconnects, switching boxes, or routers commonly found in commercially available FPGAs.

PIPBQ Effect Aware SER Analysis for Combinational Logic Circuits

Technology scaling results in the propagation-induced pulse broadening and quenching（PIPBQ） effect become more noticeable.In order to effectively evaluate the soft error rate for combinational logic circuits,a soft error rate analysis approach considering the PIPBQ effect is proposed.As different original pulse propagating through logic gate cells,pulse broadening and quenching are measured by HSPICE.After that,electrical effect look-up tables（EELUTs） for logic gate cells are created to evaluate the PIPBQ effect.Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm.Further,by propagating pulses on these paths to simulate fault injection,the PIPBQ effect on these paths can be quantified by EELUTs.As a result,the soft error rate of circuits can be effectively computed by the proposed technique.Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method.

Soft error reliability in advanced CMOS technologies—trends and challenges

With the decrease of the device size,soft error induced by various particles becomes a serious problem for advanced CMOS technologies.In this paper,we review the evolution of two main aspects of soft error-SEU and SET,including the new mechanisms to induced SEUs,the advances of the MCUs and some newly observed phenomena of the SETs.The mechanisms and the trends with downscaling of these issues are briefly discussed.We also review the hardening strategies for different types of soft errors from different perspective and present the challenges in testing,modeling and hardening assurance of soft error issues we have to address in the future.

Partial-TMR: A New Method for Protecting Register Files Against Soft Error Based on Lifetime Analysis

High-energy particles in the space can easily cause soft error in register file(RF).As a critical structure in a processor,RF often stores data for long periods of time and is read frequently,resulting in a higher probability of spreading corrupted data to other parts of the processor.The triple modular redundancy(TMR)is a common and effective fault tolerance method that enables multi-bit error correction.Designing full TMR for all the registers could cause excessive area and power overheads.However,some registers in RF have less impact on processor reliability.Therefore,there is no need to design TMR for them.This paper designs an efficient strategy which can rate the registers in RF based on their vulnerability.Based on the proposed strategy,a new RF fault tolerance method named Partial-TMR formulates in this paper,which selectively protects more vulnerable registers against multi-bit error,and improves fault tolerance efficiency.For integer RF,Partial-TMR improves its soft error correction capability by 24.5%relative to the baseline system and 3%relative to ParShield,while for floating-point RF,the improvement comes to 5.17%and 0.58%respectively.The soft error correction capability of Partial-TMR is slightly lower than that of full TMR by 1%to 3%,but Partial-TMR significantly cuts the area and power overheads.Compared with full TMR,Partial-TMR decreases the area and power overheads by 71.6%and 64.9%,respectively.It also has little impact on the performance.Partial-TMR is a more cost-effective fault tolerance method compared with ParShield and full TMR.

Register Reallocation for Soft Error Reduction

Subsequently to the problem of performance and energy overhead, the reliability problem of the system caused by soft error has become a growing concern. Since register file（RF） is the hottest component in processor, if not well protected, soft errors occurring in it will do harm to the system reliability greatly. In order to reduce soft error occurrence rate of register file, this paper presents a method to reallocate the register based on the fact that different live variables have different contribution to the register file vulnerability（RFV）. Our experimental results on benchmarks from MiBench suite indicate that our method can significantly enhance the reliability.

Soft error generation analysis in combinational logic circuits

Reliability is expected to become a big concern in future deep sub-micron integrated circuits design.Soft error rate（SER） of combinational logic is considered to be a great reliability problem.Previous SER analysis and models indicated that glitch width has a great impact on electrical masking and latch window masking effects,but they failed to achieve enough insights.In this paper,an analytical glitch generation model is proposed.This model shows that after an inflexion point the collected charge has an exponential relationship with glitch duration and the model only introduces an estimation error of on average 2.5%.

Implementation and Analysis of Probabilistic Methods for Gate-Level Circuit Reliability Estimation

The development of VLSI technology results in the dramatically improvement of the performance of integrated circuits. However, it brings more challenges to the aspect of reliability. Integrated circuits become more susceptible to soft errors. Therefore, it is imperative to study the reliability of circuits under the soft error. This paper implements three probabilistic methods (two pass, error propagation probability, and probabilistic transfer matrix) for estimating gate-level circuit reliability on PC. The functions and performance of these methods are compared by experiments using ISCAS85 and 74-series circuits.

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.