Hardware/software co-verification platform for EOS design

Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

New Approach for Hardware/Software Embedded System Conception Based on the Use of Design Patterns

This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.

Strategic Contracting for Software Upgrade Outsourcing in Industry 4.0

The advent of Industry 4.0 has compelled businesses to adopt digital approaches that combine software toenhance production efficiency. In this rapidly evolving market, software development is an ongoing process thatmust be tailored to meet the dynamic needs of enterprises. However, internal research and development can beprohibitively expensive, driving many enterprises to outsource software development and upgrades to externalservice providers. This paper presents a software upgrade outsourcing model for enterprises and service providersthat accounts for the impact of market fluctuations on software adaptability. To mitigate the risk of adverseselection due to asymmetric information about the service provider’s cost and asymmetric information aboutthe enterprise’s revenues, we propose pay-per-time and revenue-sharing contracts in two distinct informationasymmetry scenarios. These two contracts specify the time and transfer payments for software upgrades. Througha comparative analysis of the optimal solutions under the two contracts and centralized decision-making withfull-information, we examine the characteristics of the solutions under two information asymmetry scenarios andanalyze the incentive effects of the two contracts on the various stakeholders. Overall, our study offers valuableinsights for firms seeking to optimize their outsourcing strategies and maximize their returns on investment insoftware upgrades.

Software for Acoustic Design

We present the СATEС software, which implements the solution to the problems of computational acoustics. The software is based on the use of the superelement method and finite element modeling algorithms, in-cluding hydrodynamic noise. The paper presents the main possibilities of software for solving acoustic design problems. .

On Software Application Database Constraint-driven Design and Development

This paper presents a methodology driven by database constraints for designing and developing(database)software applications.Much needed and with excellent results,this paradigm guarantees the highest possible quality of the managed data.The proposed methodology is illustrated with an easy to understand,yet complex medium-sized genealogy software application driven by more than 200 database constraints,which fully meets such expectations.

Scheduling Algorithm Based on Storage Capacity of Communication in Hardware/Software Integrated System

In this paper, the storage capacity of communication among cores and processors is taken into account and a maximum D-value-first algorithm is proposed. By improving the hardware parallelism in the task execution process, the maximum storage requirements for communication are minimized. Experimental results with various directed acyclic graph models showed that compared with the earliest-task-first algorithm, the storage requirements for communication were reduced by 22.46%, on average, while the average of makespan only increased by 0.82%,.

Hardware/software partitioning based on dynamic combination of maximum entropy and chaos optimization algorithm

This paper presents an algorithm that combines the chaos optimization algorithm with the maximum entropy ( COA-ME) by using entropy model based on chaos algorithm,in which the maximum entropy is used as the second method of searching the excellent solution. The search direction is improved by chaos optimization algorithm and realizes the selective acceptance of wrong solution. The experimental result shows that the presented algorithm can be used in the partitioning of hardware/software of reconfigurable system. It effectively reduces the local extremum problem,and search speed as well as performance of partitioning is improved.

Towards High-Performance Graph Processing: From a Hardware/Software Co-Design Perspective

Graph processing has been widely used in many scenarios,from scientific computing to artificial intelligence.Graph processing exhibits irregular computational parallelism and random memory accesses,unlike traditional workloads.Therefore,running graph processing workloads on conventional architectures(e.g.,CPUs and GPUs)often shows a significantly low compute-memory ratio with few performance benefits,which can be,in many cases,even slower than a specialized single-thread graph algorithm.While domain-specific hardware designs are essential for graph processing,it is still challenging to transform the hardware capability to performance boost without coupled software codesigns.This article presents a graph processing ecosystem from hardware to software.We start by introducing a series of hardware accelerators as the foundation of this ecosystem.Subsequently,the codesigned parallel graph systems and their distributed techniques are presented to support graph applications.Finally,we introduce our efforts on novel graph applications and hardware architectures.Extensive results show that various graph applications can be efficiently accelerated in this graph processing ecosystem.

A hardware/software co-optimization approach for embedded software of MP3 decoder

In order to improve the efficiency of embedded software running on processor core, this paper proposes a hard-ware/software co-optimization approach for embedded software from the system point of view. The proposed stepwise methods aim at exploiting the structure and the resources of the processor as much as possible for software algorithm optimization. To achieve low memory usage and low frequency need for the same performance, this co-optimization approach was used to optimize embedded software of MP3 decoder based on a 16-bit fixed-point DSP core. After the optimization, the results of decoding 128 kbps, 44.1 kHz stereo MP3 on DSP evaluation platform need 45.9 MIPS and 20.4 kbytes memory space. The optimization rate achieves 65.6% for memory and 49.6% for frequency respectively compared with the results by compiler using floating-point computation. The experimental result indicates the availability of the hardware/software co-optimization approach depending on the algorithm and architecture.

TikTak: A Scalable Simulator of Wireless Sensor Networks Including Hardware/Software Interaction

We present a simulation framework for wireless sensor networks developed to allow the design exploration and the complete microprocessor-instruction-level debug of network formation, data congestion, nodes interaction, all in one simulation environment. A specifically innovative feature is the co-emulation of selected nodes at clock-cycle-accurate hardware processing level, allowing code debug and exact execution latency evaluation (considering both protocol stack and application), together with other nodes at abstract protocol level, meeting a designer’s needs of simulation speed, scalability and reliability. The simulator is centered on the Zigbee protocol and can be retargeted for different node micro-architectures.

Campus Information Network Hardware System Design

The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export design, and discusses the network hardware system design and optimization for different scale universities according to different practical demand. The objective is that the network hardware system can meet the demand and have been made full use.

Maturity assessment model for aircraft collaborative design software solution

In order to assure quality and control process in the development of the aircraft collaborative design software, a maturity assessment model is proposed. The requirements designing—house of quality is designed to evaluate the maturity degree of the solution, and the evaluation results can help to manage and control the development process. Furthermore, a fuzzy evaluation method based on the minimum deviation is proposed to deal with the fuzzy information. The quantitative evaluation result of the maturity degree can be calculated by optimizing the semantic discount factor aim for the minimum deviation. Finally, this model is illustrated and analyzed by an example study of the aircraft collaborative design software.

3D Digital Design of Cranes' Structures Based on Hybrid Software Architecture

3D digital design for cranes’ structures based on hybrid software architecture of Client/Server and Browser/Server is introduced in this paper. Based on Pro/ENGINEER platform,3D parametric model family is built to allow generation of feasible configurations of cranes’ structures in Client/Server framework. Taking use of Visual C++,the second exploiting software kit provided by Pro/ENGINEER and ANSYS GUI/APDL modeling patterns,an integration method of 3D CAD and CAE is achieved,which includes regeneration of 3D parametric model,synchronous updating and analysis of FEA model. As in Browser/Server framework,the 3D CAD models of parts,components and the whole structure could also be displayed in the customer’s browser in VRML format.

Exploration on 5E Teaching Principle-based Education for the Object-oriented Software Construction Course

Most current object-oriented programming courses offered by domestic colleges and universities generally focus on the object-oriented programming language itself,i.e.,the programming grammar of the language,but ignore the design pattern.However,design patterns are essential to software engineering because they can solve common problems in software design and improve code reuse,readability,extensibility,and reliability.Our Object-oriented Software Construction Course is creative since it aims at cultivating students’object-oriented thinking as well as basic abilities required to construct high-quality,object-oriented software.Specifically,we exploit the 5E teaching principle during the education of this course,and present the whole pipeline in the paper.We also provide one case of the factory pattern to further demonstrate the implementation of the 5E teaching principle in the course.The effect of the 5E teaching principle has also been demonstrated.

A Case Study on Design Patterns and Software Defects in Open Source Software

Design patterns are object oriented software design practices for solving common design problems and they affect software quality. In this study, we investigate the relationship of design patterns and software defects in a number of open source software projects. Design pattern instances are extracted from the source code repository of these open source software projects. Software defect metrics are extracted from the bug tracking systems of these projects. Using correlation and regression analysis on extracted data, we examine the relationship between design patterns and software defects. Our findings indicate that there is little correlation between the total number of design pattern instances and the number of defects. However, our regression analysis reveals that individual design pattern instances as a group have strong influences on the number of defects. Furthermore, we find that the number of design pattern instances is positively correlated to defect priority. Individual design pattern instances may have positive or negative impacts on defect priority.

Software Metric Analysis of Open-Source Business Software

Over the past decade, open-source software use has grown. Today, many companies including Google, Microsoft, Meta, RedHat, MongoDB, and Apache are major participants of open-source contributions. With the increased use of open-source software or integration of open-source software into custom-developed software, the quality of this software component increases in importance. This study examined a sample of open-source applications from GitHub. Static software analytics were conducted, and each application was classified for its risk level. In the analyzed applications, it was found that 90% of the applications were classified as low risk or moderate low risk indicating a high level of quality for open-source applications.

Design Knowledge and Software Engineering

This paper points out various relationships between Design Knowledge and Software Engineering. After introduction of human design, the relationships between industrial Software Engineering is discussed, then further details of human design knowledge are revealed with discussions on humanistic aspects of design.

Analysis and design for architecture-based software

The technologies of software architecture are introduced, and the software analysis-and-design process is divided into requirement analysis, software architecture design and system design. Using these technologies, a model of architecture-centric software analysis and design process（ACSADP） is proposed. Meanwhile, with regard to the completeness, consistency and correctness between the software requirements and design results, the theories of function and process control are applied to ACSADP. Finally, a model of integrated development environnment （IDE） for ACSADP is propcsed. It can be demonstrated by the practice that the model of ACSADP can aid developer to manage software process effectively and improve the quality of software analysis and design.

Depth estimation system suitable for hardware design

Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor （DSP）, and application specific integrated circuit （ASIC） and field programmable gate array （FPGA） provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.

Design of a Hardware-Implemented Phase Calculating System for Feedback Control in the LHCD Experiments on EAST

A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive （LHCD） experiments is presented in this paper. By taking advantages of field programmable gate array （FPGA） chips with embedded digital signal processing （DSP） cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave （LHW） system on EAST.