Statistical static timing analysis for circuit aging prediction

Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit reliability.BTI results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic circuits.The amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design time.In this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI degradation.It consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability distributions.This method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.

On modeling the digital gate delay under process variation

To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost,we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms.In this work,two gate delay models for process variation considering different driving and loading conditions are proposed.From the testing results,these two models,especially the one that combines effective dimension reduction（EDR） from statistics society with comprehensive gate delay models,offer good accuracy with low characterization cost,and they are thus competent for use in statistical timing analysis（SSTA）.In addition, these two models have their own value in other SSTA techniques.