When the circuit breaker cuts the electric current, an electric arc is created between its electrodes. The success or failure of breaking the electric current by the circuit breaker depends strongly on the physico-che...When the circuit breaker cuts the electric current, an electric arc is created between its electrodes. The success or failure of breaking the electric current by the circuit breaker depends strongly on the physico-chemical properties of the electric arc created, such as the composition of which depends on the material of the electrical contacts. In this work, we determine the equilibrium composition of the electric arc in the low voltage air circuit breaker with silver tin dioxide alloy contacts, in a temperature range from 500 K to 15,000 K and at atmospheric pressure. We use the Gibbs free energy minimization method and develop a computer code to determine the equilibrium composition of the created plasma. The analysis of the results obtained shows that O<sub>2</sub> particles with a dissociation energy of 5.114 eV, NO with a dissociation energy of 6.503 eV, and N<sub>2</sub> dissociation 9.756 eV dissociate around 3500 K, 5000 K, and 7500 K, respectively. We note that the electro-neutrality is established between the electrons and the cations: Ag<sup>+</sup> and NO<sup>+</sup>, for temperatures lower than 6500 K. For temperatures higher than 6500 K, the electro-neutrality is established between the electrons and the cations: N<sup>+</sup>, O<sup>+</sup>, and Ag<sup>+</sup>. The numerical density of the electrons increases when the proportion of the vapor of the electrical contacts increases in the mixture, in particular for temperatures lower than 11,000 K.展开更多
Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the c...Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.展开更多
This paper presents the design and simulation of several fixed-tuned sub-harmonic mixers cover frequencies from 110 GH to 130 GHz, 215 GH to 235 GHz, 310 GH to 350 GHz, and 400 GH to 440 GHz. Among them, 120 GHz, 225 ...This paper presents the design and simulation of several fixed-tuned sub-harmonic mixers cover frequencies from 110 GH to 130 GHz, 215 GH to 235 GHz, 310 GH to 350 GHz, and 400 GH to 440 GHz. Among them, 120 GHz, 225 GHz, 330 GHz subharmonic mixers are designed with flip-chipped planar schottky diode mounted onto a suspended quartz-based substrate, the 225 GHz and 425 GHz subharmonic mixers are GaAs membrane integrated, and the 115 GHz subharmonic mixer has been fabricated and tested already.展开更多
Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The ...Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.展开更多
This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the perfo...This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.展开更多
文摘When the circuit breaker cuts the electric current, an electric arc is created between its electrodes. The success or failure of breaking the electric current by the circuit breaker depends strongly on the physico-chemical properties of the electric arc created, such as the composition of which depends on the material of the electrical contacts. In this work, we determine the equilibrium composition of the electric arc in the low voltage air circuit breaker with silver tin dioxide alloy contacts, in a temperature range from 500 K to 15,000 K and at atmospheric pressure. We use the Gibbs free energy minimization method and develop a computer code to determine the equilibrium composition of the created plasma. The analysis of the results obtained shows that O<sub>2</sub> particles with a dissociation energy of 5.114 eV, NO with a dissociation energy of 6.503 eV, and N<sub>2</sub> dissociation 9.756 eV dissociate around 3500 K, 5000 K, and 7500 K, respectively. We note that the electro-neutrality is established between the electrons and the cations: Ag<sup>+</sup> and NO<sup>+</sup>, for temperatures lower than 6500 K. For temperatures higher than 6500 K, the electro-neutrality is established between the electrons and the cations: N<sup>+</sup>, O<sup>+</sup>, and Ag<sup>+</sup>. The numerical density of the electrons increases when the proportion of the vapor of the electrical contacts increases in the mixture, in particular for temperatures lower than 11,000 K.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2
文摘Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.
基金supported by the National Natural Science Foundation of China under Grant No.61301051
文摘This paper presents the design and simulation of several fixed-tuned sub-harmonic mixers cover frequencies from 110 GH to 130 GHz, 215 GH to 235 GHz, 310 GH to 350 GHz, and 400 GH to 440 GHz. Among them, 120 GHz, 225 GHz, 330 GHz subharmonic mixers are designed with flip-chipped planar schottky diode mounted onto a suspended quartz-based substrate, the 225 GHz and 425 GHz subharmonic mixers are GaAs membrane integrated, and the 115 GHz subharmonic mixer has been fabricated and tested already.
文摘Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2<sup>2</sup> = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.
文摘This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.
