针对极化码在中短码长时纠错性能的不足,提出了一种基于错误集的极化码改进串行抵消列表(Successive Cancellation List of Polar Codes Based on Error Set,ES-SCL)译码算法。该算法首先根据极化码的信道特性构造错误集,在极化码编码...针对极化码在中短码长时纠错性能的不足,提出了一种基于错误集的极化码改进串行抵消列表(Successive Cancellation List of Polar Codes Based on Error Set,ES-SCL)译码算法。该算法首先根据极化码的信道特性构造错误集,在极化码编码时根据错误集中的元素设置奇偶校验(Parity Check,PC)位,其余位置则放置信息比特和冻结比特,译码器在译码PC位时,每条路径通过校验函数得到PC位的比特估计,不执行路径分裂和剪枝,其余位置则执行SCL译码。仿真结果表明,在加性高斯白噪声信道下,当码长为512,码率为0.5,误块率为10^(-5),最大译码列表数为8时,相较于PC-PSCL译码算法以及CA-SCL译码算法,所提出的ES-SCL译码算法获得了约0.18和0.15 dB的增益;当码长为256,码率为0.5,误码率为10^(-5),最大译码列表数为8时,相较于CA-SCL,PC-PSCL译码算法,获得了约0.3和0.35 dB的增益;此外,采用部分比特分裂译码的ES-SCL译码算法可以在误块率与PC-PSCL译码算法几乎相同的情况下,减少约50%的排序次数,具有更低的译码复杂度。展开更多
针对基于路径分裂策略辅助极化码串行抵消列表(Path Splitting Selecting strategy based on Search Set under the Successive Cancellation List,PSS-SS-SCL)译码算法性能的不足,提出了一种利用增强型奇偶校验码改进PSSSS-SCL译码算法...针对基于路径分裂策略辅助极化码串行抵消列表(Path Splitting Selecting strategy based on Search Set under the Successive Cancellation List,PSS-SS-SCL)译码算法性能的不足,提出了一种利用增强型奇偶校验码改进PSSSS-SCL译码算法的EPC-MS-SCL(Enhanced Parity Check and Monte Carlo Segment aided Successive Cancellation List)译码算法.该算法在极化码编码阶段对信息序列做分段处理,在每段末尾添加增强型奇偶校验码,译码器仅在译码搜索集内元素时进行路径分裂,其余元素直接执行硬判决译码,并在译码完一段序列后立即对该段进行校验,仅保留通过校验的路径,从而减少了错误路径对正确路径的竞争,使正确路径保留到译码结束的概率增加,改善了译码性能,同时减少了译码列表数,使得译码复杂度更低.仿真结果表明,与PSS-SS-SCL译码算法相比较,所提出算法能在一定程度上改善其性能增益且具有更低的译码复杂度.展开更多
Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel...Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.展开更多
文摘针对极化码在中短码长时纠错性能的不足,提出了一种基于错误集的极化码改进串行抵消列表(Successive Cancellation List of Polar Codes Based on Error Set,ES-SCL)译码算法。该算法首先根据极化码的信道特性构造错误集,在极化码编码时根据错误集中的元素设置奇偶校验(Parity Check,PC)位,其余位置则放置信息比特和冻结比特,译码器在译码PC位时,每条路径通过校验函数得到PC位的比特估计,不执行路径分裂和剪枝,其余位置则执行SCL译码。仿真结果表明,在加性高斯白噪声信道下,当码长为512,码率为0.5,误块率为10^(-5),最大译码列表数为8时,相较于PC-PSCL译码算法以及CA-SCL译码算法,所提出的ES-SCL译码算法获得了约0.18和0.15 dB的增益;当码长为256,码率为0.5,误码率为10^(-5),最大译码列表数为8时,相较于CA-SCL,PC-PSCL译码算法,获得了约0.3和0.35 dB的增益;此外,采用部分比特分裂译码的ES-SCL译码算法可以在误块率与PC-PSCL译码算法几乎相同的情况下,减少约50%的排序次数,具有更低的译码复杂度。
文摘针对基于路径分裂策略辅助极化码串行抵消列表(Path Splitting Selecting strategy based on Search Set under the Successive Cancellation List,PSS-SS-SCL)译码算法性能的不足,提出了一种利用增强型奇偶校验码改进PSSSS-SCL译码算法的EPC-MS-SCL(Enhanced Parity Check and Monte Carlo Segment aided Successive Cancellation List)译码算法.该算法在极化码编码阶段对信息序列做分段处理,在每段末尾添加增强型奇偶校验码,译码器仅在译码搜索集内元素时进行路径分裂,其余元素直接执行硬判决译码,并在译码完一段序列后立即对该段进行校验,仅保留通过校验的路径,从而减少了错误路径对正确路径的竞争,使正确路径保留到译码结束的概率增加,改善了译码性能,同时减少了译码列表数,使得译码复杂度更低.仿真结果表明,与PSS-SS-SCL译码算法相比较,所提出算法能在一定程度上改善其性能增益且具有更低的译码复杂度.
文摘Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit designs.Positive Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage comparator.NMOS is used to reduce stacking leakage as well as total exchange.Domino Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent years.In this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino circuit.The efficiency and effec-tiveness of the domino circuit are demonstrated through simulation results.The suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of power.The proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR gates.As per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.
