为了提高通信系统的保密性,降低制造成本,需要进行专用处理器的设计。该文基于SELP(Sinusoidal Excitation Linear Prediction)算法模型原理,设计了一款高质量多速率语音专用处理器芯片。芯片使用可重构体系结构和超长指令字系统设计方...为了提高通信系统的保密性,降低制造成本,需要进行专用处理器的设计。该文基于SELP(Sinusoidal Excitation Linear Prediction)算法模型原理,设计了一款高质量多速率语音专用处理器芯片。芯片使用可重构体系结构和超长指令字系统设计方法,将复杂度高的子程序进行优化,能够显著提高指令并行度。仿真结果表明:在该芯片上实现语音压缩编码算法,执行效率高于相同工艺水平的通用数字信号处理器,并保持原有编码质量。该处理器能够实现多种类型的语音压缩算法,使语音算法可以达到高保密性、低复杂度和易开发性。展开更多
New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architect...New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architectures axe Configurable System-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.展开更多
文摘为了提高通信系统的保密性,降低制造成本,需要进行专用处理器的设计。该文基于SELP(Sinusoidal Excitation Linear Prediction)算法模型原理,设计了一款高质量多速率语音专用处理器芯片。芯片使用可重构体系结构和超长指令字系统设计方法,将复杂度高的子程序进行优化,能够显著提高指令并行度。仿真结果表明:在该芯片上实现语音压缩编码算法,执行效率高于相同工艺水平的通用数字信号处理器,并保持原有编码质量。该处理器能够实现多种类型的语音压缩算法,使语音算法可以达到高保密性、低复杂度和易开发性。
文摘New reconfigurable computing architectures are introduced to overcome some of the limitations of conventional microprocessors and fine-grained reconfigurable devices （e.g., FPGAs）. One of the new promising architectures axe Configurable System-on-Chip （CSoC） solutions. They were designed to offer high computational performance for real-time signal processing and for a wide range of applications exhibiting high degrees of parallelism. The programming of such systems is an inherently challenging problem due to the lack of an programming model. This paper describes a novel heterogeneous system architecture for signal processing and data streaming applications. It offers high computational performance and a high degree of flexibility and adaptability by employing a micro Task Controller （mTC） unit in conjunction with programmable and configurable hardware. The hierarchically organized architecture provides a programming model, allows an efficient mapping of applications and is shown to be easy scalable to future VLSI technologies. Several mappings of commonly used digital signal processing algorithms for future telecommunication and multimedia systems and implementation results axe given for a standard-cell ASIC design realization in 0.18 micron 6-layer UMC CMOS technology.
