Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance archit...Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.展开更多
Pixel-parallel PE and SIMD architectures are widely used in high-speed image processing to enhance computing power. With fully exploiting the data level parallelism of low- and middle-level image processing, SIMD arch...Pixel-parallel PE and SIMD architectures are widely used in high-speed image processing to enhance computing power. With fully exploiting the data level parallelism of low- and middle-level image processing, SIMD architecture is able to finish great amount of computation with much less instruction cycle thus satisfy the high-speed system requirement. The main computation parts in those SIMD image processing hardware is known as PE (processing element) and it is responsible for transferring, storing and processing the image data. This paper describes a high-speed vision system with superscalar PE to enhance system performance and its dedicated parallel computing language specifically devel-oped for this vision system. The vision system can achieve motion detection at more than 2000fps and face detection at more than 100 fps which overwhelms some general serial CPUs in the same applications.展开更多
A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of co...A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of constant current （CC） power supply could be changed according to transient physical state, and the variable down slope rate control could be used to ensure a stable welding process. The welding experiment results proved the effectiveness of this control approach.展开更多
Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management me...Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity 11 CPU of Peking University, and introduces in detail the solution of pure hardware table walking with two level page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the XWindow system, GNOME and most application software onto the Unity platform.展开更多
The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an a...The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an additional automated system of unified templates necessary for the occurrence of “trainability” elements. The templates will be formed via a separate dedicated channel for transmission, processing and storage of the necessary information, not related to the operation of the terminal, with its subsequent visualization at the workplace of the duty personnel of traction substations, together with information from the “GID” software received via another dedicated wired channel. With the help of such a base of unified preset templates, in the future, it will be possible not only to identify the specific causes of each emergency shutdown but also to reduce their number by dynamically adjusting the existing presets of the standard operation algorithm.展开更多
This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed...This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper.展开更多
We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss sta...We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss statistics at runtime using an extra tag array. These executing statistics serve as inputs to an analytical model of cache energy. The scheme uses energy as a primary metric to dynamically increase/decrease the number of active cache ways for the next interval. The scheme minimizes the active cache size to save energy with minimal performance loss. The simulation with SPEC 2000 benchmarks shows that OCR results in an average of 38.4% energy saving compared with fixed-size caches, with only 2.0% performance loss.展开更多
In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by usin...In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation;this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.展开更多
The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. R...The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. Real statistics on the number of microprocessor relay protection operations at the Buryatskaya traction substation are presented, simulation of the real train situation (in accordance with the regime maps of the throughput capacity of the sections of the Trans-Baikal railway) was carried out in the specialized software complex “KORTES”. Based on the results of the analysis of simulation modeling, the process of forming a unified template of settings using neural network technologies is considered, which characterizes only this specific regular train situation. To protect objects in the event of pre-emergency and emergency modes of operation of the traction power supply system, a variant of changing the standard operation algorithm of the TsZA-27.5-FKS (FTS) terminal by introducing additional blocks for calculating the predictive functions of current and voltage has been proposed.展开更多
UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and t...UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and temperature correct are realized,The wavelength tuned output efficiency in the experiment is better than 97 %.展开更多
This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filte...This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filter to remove these two normal noise signals. Signal from the MIT-BIH electrocardiogram database was used to test the performance of the filter. From the test results, the performance of the digital filer is reDT good. The filter coefficient is an integer number, therefore, the filtering algorithm can be successfully implemented on the microprocessor.展开更多
Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can ...Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can leak sensitive user data and information.This report will investigate microarchitecture vulnerabilities focusing on the Spectre and Meltdown exploits and will look at what they do,how they do it and,the real-world impact these vulnerabilities can cause.Additionally,there will be an introduction to the basic concepts of how several PC components operate to support this.展开更多
Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermo...Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermore,in this paper we discuss the validity of instruction prefetch,the branch prediction,the depth of instruction window and other issues that can affect the performance of superscalar DSP.展开更多
文摘Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.
文摘Pixel-parallel PE and SIMD architectures are widely used in high-speed image processing to enhance computing power. With fully exploiting the data level parallelism of low- and middle-level image processing, SIMD architecture is able to finish great amount of computation with much less instruction cycle thus satisfy the high-speed system requirement. The main computation parts in those SIMD image processing hardware is known as PE (processing element) and it is responsible for transferring, storing and processing the image data. This paper describes a high-speed vision system with superscalar PE to enhance system performance and its dedicated parallel computing language specifically devel-oped for this vision system. The vision system can achieve motion detection at more than 2000fps and face detection at more than 100 fps which overwhelms some general serial CPUs in the same applications.
基金Supported by Research Project of Henan Science and Technology Foundation(0124110209,0211061900).
文摘A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of constant current （CC） power supply could be changed according to transient physical state, and the variable down slope rate control could be used to ensure a stable welding process. The welding experiment results proved the effectiveness of this control approach.
文摘Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity 11 CPU of Peking University, and introduces in detail the solution of pure hardware table walking with two level page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the XWindow system, GNOME and most application software onto the Unity platform.
文摘The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an additional automated system of unified templates necessary for the occurrence of “trainability” elements. The templates will be formed via a separate dedicated channel for transmission, processing and storage of the necessary information, not related to the operation of the terminal, with its subsequent visualization at the workplace of the duty personnel of traction substations, together with information from the “GID” software received via another dedicated wired channel. With the help of such a base of unified preset templates, in the future, it will be possible not only to identify the specific causes of each emergency shutdown but also to reduce their number by dynamically adjusting the existing presets of the standard operation algorithm.
文摘This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper.
基金The High Technology Research and Development Program of China (No.2006AA01Z226)the Natural Science Foundation of Hubei (No.2007ABD002)the Ministry of Education-INTEL Information Technology Foundation (No.MOE-INTEL-08-05)
文摘We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss statistics at runtime using an extra tag array. These executing statistics serve as inputs to an analytical model of cache energy. The scheme uses energy as a primary metric to dynamically increase/decrease the number of active cache ways for the next interval. The scheme minimizes the active cache size to save energy with minimal performance loss. The simulation with SPEC 2000 benchmarks shows that OCR results in an average of 38.4% energy saving compared with fixed-size caches, with only 2.0% performance loss.
文摘In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation;this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.
文摘The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. Real statistics on the number of microprocessor relay protection operations at the Buryatskaya traction substation are presented, simulation of the real train situation (in accordance with the regime maps of the throughput capacity of the sections of the Trans-Baikal railway) was carried out in the specialized software complex “KORTES”. Based on the results of the analysis of simulation modeling, the process of forming a unified template of settings using neural network technologies is considered, which characterizes only this specific regular train situation. To protect objects in the event of pre-emergency and emergency modes of operation of the traction power supply system, a variant of changing the standard operation algorithm of the TsZA-27.5-FKS (FTS) terminal by introducing additional blocks for calculating the predictive functions of current and voltage has been proposed.
文摘UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and temperature correct are realized,The wavelength tuned output efficiency in the experiment is better than 97 %.
文摘This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filter to remove these two normal noise signals. Signal from the MIT-BIH electrocardiogram database was used to test the performance of the filter. From the test results, the performance of the digital filer is reDT good. The filter coefficient is an integer number, therefore, the filtering algorithm can be successfully implemented on the microprocessor.
文摘Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can leak sensitive user data and information.This report will investigate microarchitecture vulnerabilities focusing on the Spectre and Meltdown exploits and will look at what they do,how they do it and,the real-world impact these vulnerabilities can cause.Additionally,there will be an introduction to the basic concepts of how several PC components operate to support this.
文摘Under the direction of design space theory,in this paper we discuss the design of a superscalar pipelining using the way of multiple issues,and the implement of a superscalar based RISC DSP architecture,SDSP.Furthermore,in this paper we discuss the validity of instruction prefetch,the branch prediction,the depth of instruction window and other issues that can affect the performance of superscalar DSP.
