Influences of supply voltage on single event upsets and multiple-cell upsets in nanometer SRAM across a wide linear energy transfer range

The influences of reducing the supply voltage on single event upset(SEU) and multiple-cell upset(MCU) in two kinds of 65-nm static random access memories(SRAMs) are characterized across a wide linear energy transfer(LET) range.The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6 T SRAM or radiation-hardened double dual interlocked cells(DICE) SRAM.When the LET value is lower than the LET threshold of MCU,the SEU only manifests single cell upset,the SEU cross section increases with the decrease of voltage.The lower the LET value,the higher the SEU sensitivity to the voltage variation is.Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU.Moreover,the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range.With further scaling the feature size of devices down,it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf(COTS) SRAM.

Application of a Current and Voltage Mixed Control Mode for the New Fast Control Power Supply at EAST

A feedback control system is needed to restrain plasma vertical displacement in EAST （Experimental Advanced Superconducting Toknmak）. A fast control power supply excites active feedback coils, which produces a magnetic field to control the plasma＇s displacement. With the development of EAST, new demands on the new fast control power supply have led to an enhanced ability of fast response and output current, as well as a new control mode. The structure of cascaded and paralleled H-bridges can meet the demand of extended capacity, and digital control can reMize current and voltage mixed control mode. The validity of the proposed scheme is confirmed by experiments.

Experiment and Operation of a LHCD-35kV/2.8MW/1000s High-Voltage Power Supply on HT-7 Tokamak

A -35 kV/2.8 MW/1000s high-voltage power supply (HVPS) for HT-7 superconducting tokamak has been built successfully. The HVPS is scheduled to run on a 2.45 GHz/1 MW lower hybrid current drive (LHCD) [1] system of HT-7 superconducting tokamak before the set-up of HT-7 superconducting tokamak in 2003. The HVPS has a series of advantages such as good steady and dynamic response, logical computer program controlling the HVPS without any fault, operational panel and experimental board for data acquisition, which both are grounded distinctively in a normative way to protect the main body of HVPS along with its attached equipments from dangers. Electric power cables and other control cables are disposed reasonably, to prevent signals from magnetic interference and ensure the precision of signal transfer.This paper involves the experiment and operation of a 35 kV/2.8 MW/1000s HVPS [2] for 2.45 GHz/1 MW LHCD system. The reliability and feasibility of the HVPS has been demonstrated in comparison with experimental results of original design and simulation data.

Design and Simulation of a Electrorheological(ER) Control High Voltage Power Supply

Few applications with electrorheological （ER） fluids have been found in industry. One reason is high voltage power supplies cannot meet the requirement for ER effect. In this paper, an ER control high voltage power supply for engineering application was designed which reduced power wastage by adopting soft switch technology; lessened its volume to satisfy micromation when adopting the planar transformer and improved its response character- istic by choosing an assistant discharging circuit. Simultaneously, a simulation analysis has been carried out. As results, the output voltage of this high voltage power supply is 5 kV, and the voltage can be continuously regulated and the voltage ripple is only 0. 7 %, so the requirement of stability is also achieved.

The Design of PSM-Based ECRH Power Supply Control System

Electron cyclotron resonance heating (ECRH) system is one of the most important Tokamak auxiliary heating methods. However, there are growing demands for ECRH system as the physical experiments progress which meanwhile adds the difficulty of designing and building the control system of its power source. In this paper, the method of designing a control system based on Single Chip Microcomputer (SCM) and Field Programmable Gate Array (FPGA) is introduced according to its main requirements. The experimental results show that the control system in this paper achieves the conversion of different working modes, gets exact timing, and realizes the failure protection in 10us thus can be used in the ECRH system.

Low Voltage Direct Current Supply and Utilization System:Definition,Key Technologies and Development

With rapid increase of distributed solar power generation and direct current(DC)based loads such as data centers,electric vehicles(EVs),and DC household appliances,the development trend of the power system is changed from conventional alternate current(AC)to DC.Traditional AC power systems can scarcely meet the development demand of new DC trends,especially since both the generation side and load side are comprised of DC-based electronic power components.With this background,low voltage direct current supply and utilization system(LVDCSUS)has attracted more and more attention for its great advantages over an AC grid to overcome challenges in operation,reliability,and energy loss in renewable energy connection,DC load power utilization and a number of other aspects.However,the definition of the LVDCSUS is still not clear even though many demonstration projects have been put into planning and operation.In order to provide a clear description of LVDCSUS,first,the characteristics of LVDCSUS are illustrated in this paper to show the advance of the LVDCSUS.Second,the potential application scenarios of LVDCSUS are presented in this paper.Third,application of LVDCSUS technologies and some demonstration projects in China are introduced.Besides the development of the LVDCSUS,key technologies,including but not limited to planning and design,voltage levels,control strategies,and key equipment of LVDCSUS,are discussed in this paper.Finally,future application areas and the research orientations of LVDCSUS are analyzed.

Dependence of single event upsets sensitivity of low energy proton on test factors in 65 nm SRAM

In order to accurately predict the single event upsets （SEU） rate of on-orbit proton, the influence of the proton energy distribution, incident angle, supply voltage, and test pattern on the height, width, and position of SEU peak of low energy protons （LEP） in 65 nm static random access memory （SRAM） are quantitatively evaluated and analyzed based on LEP testing data and Monte Carlo simulation. The results show that different initial proton energies used to degrade the beam energy will bring about the difference in the energy distribution of average proton energy at the surface and sensitive region of the device under test （DUT）, which further leads to significant differences including the height of SEU peak and the threshold energy of SEU. Using the lowest initial proton energy is extremely important for SEU testing with low energy protons. The proton energy corresponding to the SEU peak shifts to higher average proton energies with the increase of the tilt angle, and the SEU peaks also increase significantly. The reduction of supply voltage lowers the critical charge of SEU, leading to the increase of LEP SEU cross section. For standard 6-transitor SRAM with bit-interleaving technology, SEU peak does not show clear dependence on three test patterns of logical checkerboard 55H, all＂ 1＂, and all ＂0＂. It should be noted that all the SEUs in 65 nm SRAM are single cell upset in LEP testing due to proton＇s low linear energy transfer （LET） value.

Investigation on latch-up susceptibility induced by high-power microwave in complementary metal–oxide–semiconductor inverter

The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.

Experimental investigation and comparative study of interturn short-circuits and unbalanced voltage supply in induction machines

A transient model for an induction machine with stator winding turn faults on a single phase is derived using reference frame transformation theory. The negative sequence component and the 3rd harmonic are often considered as accurate indicators. However, small unbalance in the supply voltage and/or in the machine structure that exists in any real system engenders the same harmonics components. In this case, it is too difficult to distinguish between the current harmonics due to the supply voltage and those originated by inter-turn short- circuit faults. For that, to have the correct diagnosis and to increase the sensitivity and the reliability of the diagnostic system, it is crucial to provide the relationship between the inter-turn short-circuits in the stator winding and the supply voltage imbalance through an accurate mathematical model and via a series of experimental essays.

A high stability high voltage power supply design for HEPS injection system

Purpose The high energy photon source(HEPS)uses the on-axial injection scheme.There are two designs in this injection scheme that are critical to the performance of the HEPS injection system.One is the strip line kicker and another is the high voltage fast pulse power supply system.In the high voltage fast pulse power supply system,the design of high voltage power supply is very important.The output voltage stability of high voltage power supply directly affects the stability of the pulse amplitude of the injection system.Methods A high voltage power supply with high output voltage stability is designed in this paper,and the scheme is given.The correctness of the design scheme is verified by simulation experiments.Result A prototype is built for full test.The test results showed that the output voltage stability is lower than 58 ppm.The output voltage is 6.4 mV(f≤3 kHz)/113.2 mV(f>3 kHz).Conclusions The designed high voltage power supply can fully meet the requirements of the HEPS injection system.

A CMOS frontend chip for implantable neural recording with wide voltage supply range

A design for a CMOS frontend integrated circuit （chip） for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier （IA） and a cyclic analog-to-digital converter （CADC）. The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits （ENOB） of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 （including pads）. In-vitro recording was successfully carried out by the proposed frontend chip.

Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs

To reduce the interconnect delay and improve the chip performance, three-dimensional （3D） chip emerged with the rapid increasing of chip integration and chip power density. Therefore, thermal issue is one of the critical challenges in 3D IC design due to the high power density. Multiple Supply Voltages （MSV） technique provides an efficient way to optimize power consumption which in turn may alleviate the hotspots. But the voltage assignment is limited not only by the performance constraints of the design, but also by the physical layout of circuit modules since the modules with the same voltage should be gathered to reduce the power-network routing resource. Especially in 3D designs, the optimization using MSV technique becomes even more complicated since the high temperature also influences the power consumption and delay on paths. In this paper, we address the voltage-island generation problem for MSV designs in 3D ICs based on a mixed integer linear programming （MILP） model. First, we propose a general MILP formulation for voltage-island generation to optimize thermal distribution as well as power-network routing resources while maintaining the whole chip performance. With the thermal^power interdependency, an iterative optimization approach is proposed to obtain the convergence. Experimental results show that our thermal-aware voltage-island generation approach can reduce the maximal on-chip temperature by 23.64% with a reasonable runtime and save the power-network routing resources by 16.71%.

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

This paper proposes a novel high-power supply rejection ratio（high-PSRR） high-order curvature-compensated CMOS bandgap voltage reference（BGR） in SMIC 0.18 μm CMOS process. Three kinds of current are added to a conventional BGR in order to improve the temperature drift within wider temperature range, which include a piecewise-curvaturecorrected current in high temperature range, a piecewise-curvature-corrected current in low temperature range and a proportional-to-absolute-temperature T^（1.5） current. The high-PSRR characteristic of the proposed BGR is achieved by adopting the technique of pre-regulator. Simulation results shows that the temperature coefficient of the proposed BGR with pre-regulator is 8.42x10^（-6）′ /℃ from - 55 ℃ to 125 ℃ with a 1.8 V power supply voltage. The proposed BGR with pre-regulator achieves PSRR of - 123.51 dB, - 123.52 dB, - 88.5 dB and - 50.23 dB at 1 Hz, 100 Hz, 100 kHz and 1 MHz respectively.

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.

Experimental Investigation of the Effects of Various Plasma Actuator Configurations on Lift and Drag Coefficients of a Circular Cylinder Including the Effects of Electrodes

In this paper, the effects of the existence of plasma actuator electrodes and also various configurations of the actuator for controlling the flow field around a circular cylinder are experimentally investigated. The cylinder is made of PVC （Polyvinyl Chloride） and considered as a dielectric barrier. Two electrodes are fiush-mounted on the surface of the cylinder and are connected to a DC high voltage power supply lbr generation of electrical discharge. Pressure distribution results show that the existence of the electrodes and also the plasma are able to change the pressure distribution around the cylinder and consequently the lili and drag coefficients. It is found that the effect of the existence of the electrodes is comparable with the effect of plasma actuator in con- trolling the flow field around the cylinder and this effect is not reported by other researchers. Eventually it is concluded that the existence of the electrodes or any extra obiects on the cylinder and also the existence of the plasma are capable of changing the flow field structure around the cylinder so that the behavior of the lift and drag coefficients of the cylinder will be changed significantly.

Machining of circular micro holes by electrochemical micro-machining process

Machining of micro holes with micro electro- chemical machining （micro ECM） process has been carried out with an indigenously developed set up. This paper describes relevant problems and solutions for the circular micro holes machining process on 304 stainless steel sheets with 60 μm thickness using high speed steel cylindrical tool of diameter 500 ~tm and using dilute I-I2SO4 as elec- trolyte. The taper angle variation of the machined hole is analyzed and reported for different experimental setting parameters. The minimum value of the taper angle of machined holes is achieved at the parameter setting of 0.4 mol/L H2504, 700 kHz, 600 ns and 21 V, for stainless steel sheets and HSS tool.