Direct on Line Starting Induction Motor with Thyristor Switched Capacitor Based Voltage Regulation

The purpose of this paper is to show a laboratory scale implementation of a Thyristor Switched Capacitors （TSC） as an alternative for voltage regulation during a direct on line three-phase induction motor starting on an emulated weak transmission line. Thyristor switched capacitor bank was chosen because it is a well known topology, considering the very nature of the direct starting induction motors, which represents a highly inductive load, the use of switched reactors becomes unnecessary. Such fact minimizes the introduction of harmonics components, and also reduces the cost of the implementation. The binary disposition of the banks allows a variable Var compensation with sixteen steps, in this case. The solution makes use of low cost devices combined with sliding window voltage and current measurement algorithm and a PI control with dead band control for achieve the shown experimental results, where the system is able to manage a typically 20% voltage drop, reducing it to less than 4%. The schematic of the developed circuit, the control technique and a quite simple method to calculate the binary weight capacitors banks are also presented.

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator（VCO） with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents （~ 4 mA max） and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS （Mega-samples per Second） and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.

A Switched Capacitor Harmonic Compensation Part for Switching Supplies

A new approach based on switched capacitor network to harmonic compensation for switching supplies is presented in the paper. The basic principle is discussed. SPICE simulation is applied to analyze the behaviour of the switched capacitor harmonic compensation part.

A novel switched capacitor bandgap reference with a correlated double sampling structure

A switched capacitor bandgap voltage reference with correlated double sampling structure embedded in a temperature sensor is implemented in a standard 0.35 um CMOS process. Due to the smaller change of the op-amp＇s output voltage, this topology is very suitable for low power applications. In addition, errors caused by the finite op-amp gain, input offset voltage, and 1/f noise are eliminated with the correlated double sampling technique. Additionally, two-level process calibration techniques are designed to minimize the process spread. Finally, a method of getting a full period valid reference voltage output is discussed and experimental results are provided to verify the effectiveness of the proposed structure.

Non-isolated Step-up DC-DC Converter Based on Switched Capacitor Cells

A non-isolated high gain step-up DC-DC converter for low power applications is suggested in this study.In the designed transformerless converter,the main switch current and voltage stress is reduced while maintaining high voltage gain.For instance,with a duty cycle of 0.5 a voltage gain equal to 5 is achieved while the normalized switch voltage stress is 0.4.Also,it decreases power losses of active and passive elements.In the proposed converter design,the switched-capacitor(SC)technique is used to obtain maximum voltage transfer gain using only one switch.The three modes of operation,i.e.,continuous conduction mode(CCM),boundary conduction mode(BCM),and discontinuous conduction mode(DCM),are studied in detail.The small signal analysis(SSA)of the designed converter is investigated,and its steady-state model is examined under CCM.Performance of the proposed converter proposed in this study is assessed and tested using a prototype.Efficiency of the converter is recorded above 94%in a wide range of output powers.Overall,compared to the other converters,the results suggest satisfactory performance of the designed converter.An issue of the proposed converter is that its input current is not smooth due to using the switched-capacitor cell in its structure.This issue is alleviated by using input filters.

A Novel Dual-Rate Sampling Switched-Capacitor Configuration and Its Application

In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.

Multi-Phase QR ZCS Switched-Capacitor Bidirectional Power Converter for PV System Application

The multi-phase implementation in the QR （quasi resonant） ZCS （zero current switching） SC （switched capacitor） bidirectional DC-DC converter structure has been proposed to reduce current ripple, switching loss and significantly increase the converter efficiency and power density. This approach provides a more precise output voltage to obtain voltage conversion ratios from the double-mode versus half-mode to n-mode versus 1/n mode. This is accomplished by adding a different number of switched-capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes. The size and cost can be reduced when the proposed converter has been designed with the coupled inductors. The simulation and experimental results have been used to demonstrate the performance of the two-phase with and without coupled inductor interleaved QR ZCS SC converters for bidirectional power flow control application, and an extending structure for N-phase is mentioned.

A Design of the Elliptic Switched Current Filter

In conformity with a fifth order RLC elliptic filter circuit prototype, it is easy to conceive the corresponding RC active filter circuit. Simple and feasible method presented here can be used to contrive the equivalent switched capacitor filter circuit and switched current filter circuit. Consulting the technique data manual, we can expediently design a specific RLC filter. Therefore, it is of great convenience to design the switched current filter, which has the same performances. Such a kind of technology is useful in the domain of analogue sampled data signal processing.

Capacitor Pattern H-Bridge Multilevel Inverter (CPHMLI) Using Phase Diposition Pulse Width Modulation for Grid Applications

This work presents an implementation of an innovative single phase multilevel inverter using capacitors with reduced switches. The proposed Capacitor pattern H-bridge Multilevel Inverter (CPHMLI) topology consists of a proper number of Capacitor connected with switches and power sources. The advanced switching control supplied by Pulse Width Modulation (PDPWM) to attain mixed staircase switching state. The charging and discharging mode are achieved by calculating the voltage error at the load. Furthermore, to accomplish the higher voltage levels at the output with less number of semiconductors switches and simple commutation designed using CPHMLI topology. To prove the performance and effectiveness of the proposed approach, a set of experiments performed under various load conditions using MATLAB tool.

Switching of Capacitors in an Asymmetric Induction Motor with Single-Phase Power,Triggering Several Applied Loads

xThis study has as its objective to collaborate with the expansion in the market of electric energy in rural areas,offering as such an innovative prospect to the solution of associated problems through use of the asymmetric three-phase induction motor,supplied by a single-phase source.In this system,capacitor switching is applied during operation,while theoretical and practical results are presented for the application of this switching in a three-phase asymmetric induction motor of 20 hp.

Composite Converter Combined APFC with Switched-capacitor Converter

To reduce switch numbers and voltage stress in semiconductor devices,this paper proposes a novel single-phase converter combined Active Power Factor Correction(APFC)with switched-capacitor converter.In addition,dynamic voltage regulation and voltage gain are improved by integrating the boost converter and switching capacitor cells.The interstage bulk capacitor is no longer needed.An average current control with redistribution of voltage in cells is proposed to obtain voltage lift ability of the switching capacitor cells and maintain a high-power factor.To study and verify the proposed converter preliminarily,theoretical analysis and simulation are presented in the paper.Furthermore,a 50o W prototype with two different configurations is built for experimental verification.The proposed converter can reach 95.62%of maximum efficiency,0.99 of power factor,and 3.55%of THD with 600 V output voltage,simultaneously.

CHAOTIC TRANSDUCER

Utilizing the character of chaos, the sensitivity to the initial conditions, the concept and the structure of so-called chaotic transducer based on Tent map is provided in this paper creatively. The possibility of applying the basic theory of symbolic dynamics to the measurement is presented and proved. Then, the theoretical model of chaotic transducer is realized by using the switched capacitor and the basic experimental results are given. The transducer has such characters as high sensitivity, resolution, the simple structure and combining signal amplification with A/D. The new area of the application of chaos is exploited. Meanwhile, it provides a new method of exploring the structure of new type transducer.

A 16 bit Stereo Audio ΣΔ A/D Converter

A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

A multifunctional switched-capacitor programmable gain amplifier for high-definition video analog front-ends

A multifunctional programmable gain amplifier（PGA） that provides gain and offset adjusting abilities for high-definition video analog front-ends（AFE） is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter（ADC） in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter（DAC） for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18- m process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of –220 to220 mV while consuming 10.1 mA from a 1.8 V power supply.

Generalized Switched-Capacitor Step-up Multilevel Inverter Employing Single DC Source

In this paper,a new generalized step-up multilevel DC-AC converter is proposed,which is suitable for applications with low-voltage input sources,such as photovoltaic power generation and electric vehicles.This inverter can achieve a high voltage gain by controlling the series-parallel conversion of the DC power supply and capacitors.Only one DC voltage source and a few power devices are employed.The maximum output voltage and the number of output levels can be further increased through the switched-capacitor unit’s extension and the submodule cascaded extension.Moreover,the capacitor voltages are self-balanced without complicated voltage control circuits.The complementary operating mechanism between each pair of switches simplifies the modulation algorithm.The inductiveload ability is fully taken into account in the proposed inverter.Additionally,a remarkable characteristic of the inverter is that the charging and discharging states among different capacitors are synchronous,which reduces the voltage ripple of the frontend capacitors.The circuit structure,the working principle,the modulation strategy,the capacitors and losses analysis are presented in detail.Afterwards,the advantages of the proposed inverter are analyzed by comparing with other recently proposed inverters.Finally,the steady-state and dynamic performance of the proposed inverter is verified and validated by simulation and experiment.

A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range

This paper presents a fully integrated 4 8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0 25μm SMIC CMOS process.The oscillator consumes 6mA from 2 5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4 8GHz.Measured phase noise at 1MHz away from the carrier in this 4 8GHz VCO with symmetrical noise filter is -123 66dBc/Hz.This design is suitable for the usage in a phase locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched capacitors.The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers.The selective harmonic elimination(SHE)approach is used to remove the lower-order harmonics.The optimal switching angles for SHE is determined using the genetic algorithm.These switching angles are com-bined with a level-shifted pulse width modulation(PWM)technique for pulse generation,resulting in reduced total harmonic distortion(THD).A detailed com-parison has been made against other relevant seven-level inverter topologies in terms of the number of switches,drivers,diodes,capacitors,and boosting facil-ities to emphasize the benefits of the proposed model.The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results.The Digital Signal Processing(DSP)TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

A Novel Single Switch High Gain DC-DC Converter Topology for Renewable Energy Systems

Renewable energy with sources such as photovoltaic(PV)or fuel cells can be utilized for the generation of elec-trical power.But these sources generate fewer voltage values and therefore require high gain converters to match with DC bus voltage in microgrids.These high gain converters can be implemented with switched capacitors to meet the required DC bus voltage.Switched capacitors operate in a series and parallel combination during switch-ing operation and produce high static gain,limits reverse voltage that appears across the components.A novel converter is proposed that satisfies all the features such as high voltage gain,only one switch,forces less potential stress cross the components,ripple current is less.These features of the proposed converter are verified through MATLAB/SIMULINK.