A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator（VCO） with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.

Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

SCAs （Switched Capacitor Arrays） have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents （~ 4 mA max） and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS （Mega-samples per Second） and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor.

LC voltage controlled oscillator in 0.18-μm RF CMOS

An integrated low-phase-noise voltage-controlled oscillator （VCO） has been designed and fabricated in SMIC 0.18 μm RF CMOS technology. The circuit employs an optimally designed LC resonator and a differential cross-coupling amplifier acts as a negative resistor to compensate the energy loss of the resonator. To extend the frequency tuning range, a three-bit binary-weighted switched capacitor array is used in the circuit. The testing result indicates that the VCO achieves a tuning range of 60% from 1.92 to 3.35 GHz. The phase noise of the VCO is -117.8 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz. It draws 5.6 mA current from a 1.8 V supply. The VCO integrated circuit occupies a die area of 600 × 900 μm^2. It can be used in the IEEE802.1 lb based wireless local network receiver.

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is -120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is -169 dBc/Hz.

Wide band low phase noise QVCO based on superharmonic injection locking

A wide band, injection-coupled LC quadrature voltage control oscillator is presented. In the proposed circuit, two oscillators are injection locked by coupling their second-order harmonics in anti-phase, forcing the outputs of two oscillators into a quadrature phase state. As the common-mode point sampling the second har- monic frequency, flicker noise of the tail current is suppressed, the phase noise is reduced .The proposed design accomplishes a wide tuning frequency range by a combination of using a 5-bit switch capacitor array （SCA） for discrete tuning in addition to linearly varying AMOS varactors for continuous tuning. The proposed design has been fabricated and verified in a 0.18/zm TSMC CMOS technology process. The measurement indicates that the quadrature voltage controlled oscillator has a 41.7% tuning range from 3.53 to 5.39 GHz. The measured phase noise is 127.98 dBc/Hz at 1 MHz offset at a 1.8 V supply voltage with a power consumption of 12 mW at a carrier frequency of 4.85 GHz.