Nonlinear Auto-Companding Method for Behavioral Modeling of Switched-Current Circuits

A wavelet collocation method with nonlinear auto companding is proposed for behavioral modeling of switched current circuits.The companding function is automatically constructed according to the initial error distribution obtained through approximating the input output function of the SI circuit by conventional wavelet collocation method.In practical applications,the proposed method is a general purpose approach,by which both the small signal effect and the large signal effect are modeled in a unified formulation to ease the process of modeling and simulation.Compared with the published modeling approaches,the proposed nonlinear auto companding method works more efficiently not only in controlling the error distribution but also in reducing the modeling errors.To demonstrate the promising features of the proposed method,several SI circuits are employed as examples to be modeled and simulated.

Research on Switching Characteristics Based on Optimization Design of SiC MOSFET Drive Circuit

With the increasing emphasis on energy conservation,emission reduction and environmental protection,the application prospect of SiC power devices is becoming more and more broad.In the high frequency application of SiC MOSFET,the change rate of voltage and current in the turn-on and turn-off process increases with the increase of switching frequency.Also,the current and voltage spike oscillation phenomenon is gradually intensified due to the influence of circuit stray parameters.Based on the analysis of SiC MOSFET characteristics,the paper discusses the design requirements and design principles of SiC MOSFET drive circuit.Then,taking the SiC module C2M0080120D of Cree Company as an example,a driver circuit design is realized through the ACPL-355JC optocoupler driver module of Broadcom Company.The circuit not only has the characteristics of fast transmission delay and excellent performance,but also has the functions of overload and short circuit protection.The driving circuit is verified by LTspice simulation software,and the switching characteristics of SiC MOSFET under different working conditions are studied in depth.The experimental results show that the driving circuit can improve the switching time of SiC MOSFET and effectively solve the problem of current and voltage spike oscillation,which lays a foundation for the practical application of SiC MOSFET in the future.

Three Dimensional Electric Circuits with Multiple Capacitors and Resistors

Two cubical 3D electric circuits with single and double capacitors and twelve ohmic resistors are considered. The resistors are the sides of the cube. The circuit is fed with a single internal emf. The charge on the capacitor(s) and the current distributions of all twelve sides of the circuit(s) vs. time are evaluated. The analysis requires solving twelve differential-algebraic intertwined symbolic equations. This is accomplished by applying a Computer Algebra System (CAS), specifically Mathematica. The needed codes are included. For a set of values assigned to the elements, the numeric results are depicted.

Design of a Switched Capacitor Negative Feedback Circuit for a Very Low Level DC Current Amplifier

To miniaturize a very low level dc current amplifier and to improve its output response speed, the switched capacitor negative feedback circuit (SCNF), instead of the conventionally used high-ohmage resistor, is presented in this paper. In our system, a switched capacitor filter (SCF) and an offset controller are also used to decrease vibrations and offset voltage at the output of the amplifier using SCNF. The theoretical output voltage of the very low level dc current amplifier using SCNF is obtained. The experimental results show that the unnecessary components of the amplifier’s output are much decreased, and that the response speed of the amplifier with both the SCNF and SCF is faster than that using high-ohmage resistor.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

DESIGN OF TERNARY CURRENT-MODE CMOS CIRCUITS BASED ON SWITCH-SIGNAL THEORY

By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.

Waveform digitization utilizing switched-capacitor arrays

Compared with traditional waveform digitization with flash-ADCs, waveform digitization with switched-capacitor arrays (SCAs) is able to achieve the sampling speed above 1 GS/s without degrading the analog to digital conversion precision significantly. In this paper, we present the implementation of a fast waveform digitization system with the use of SCAs, and evaluate its performance of waveform digitization and the waveform timing. At about 5 GS/s, the dynamic input range of the digitizer is about 66 dB, and its timing precision is about 20 ps (RMS).

Tunable Bandwidth Third Order Switched-Capacitor with Multiple Feedbacks Filter for Different Center Frequencies

This paper proposes third order tunable bandwidth active Switched-Capacitor filter. The circuit consists of only op-amps and switched capacitors. The circuit is designed for circuit merit factor Q = 10. The proposed circuit implements three filter functions low pass, band pass and high pass simultaneously in single circuit. The filter circuit can be used for both narrow as well as for wide bandwidth. For various values of cut-off frequencies the behaviour of circuit is studied. The circuit works properly only for higher central frequencies, when f0 > 10 kHz.

Full Graph Methods of Switched Current Circuit Solution

Circuits with switched current are described by an admittance matrix and seeking current transfers then means calculating the ratio of algebraic supplements of this matrix. As there are also graph methods of circuit analysis in addition to algebraic methods, it is clearly possible in theory to carry out an analysis of the whole switched circuit in two-phase switching exclusively by the graph method as well. For this purpose it is possible to plot a Mason graph of a circuit, use transformation graphs to reduce Mason graphs for all the four phases of switching, and then plot a summary graph from the transformed graphs obtained this way. First the author draws nodes and possible branches, obtained by transformation graphs for transfers of EE （even-even） and OO （odd-odd） phases. In the next step, branches obtained by transformation graphs for EO and OE phase are drawn between these nodes, while their resulting transfer is 1 multiplied by z^1/2. This summary graph is extended by two branches from input node and to output node, the extended graph can then be interpreted by the Mason＇s relation to provide transparent current transfers. Therefore it is not necessary to compose a sum admittance matrix and to express this consequently in numbers, and so it is possible to reach the final result in a graphical way.

Design of Sixth-Order Lowpass Elliptic Switched-Capacitor Filter

In this paper the design and implementation of sixth-order lowpass elliptic switched-capacitor filter( SCF) for interface circuit of Micro-Electro-Mechanical System( MEMS) sensor are presented. This work aims to lower total harmonic distortion( THD) without deteriorating other performances. After system design in Simulink,the filter is realized in transistor level and finally fabricated in Central Semiconductor Manufacturing Corporation( CSMC) 0.5 μm metal-oxide-semiconductor( CMOS) technology. Typical measured results are: it operates with 25: 1 clock-to-corner frequency ratio and a 10 k Hz maximum corner frequency. The maximum passband ripple is about 0.49 d B and the minimum stopband rejection is 40 d B for the temperature from-20 ℃to 80 ℃. For the 250 k Hz clock frequency setting,given the 1 k Hz,- 8 d BVrms input signal,the measured worst case THD is-64 d B. The active area of the chip is 2.8 mm2 with 8 pads. The analog power dissipation is10 m W from a 5 V power supply.

NOVEL LINEAR TRANSFORMATION SWITCHED-CAPACITOR FILTER DESIGN

This paper presents a novel method that is applied to realize the Linear Transformation(LT)Switched-Capacitor Filter(SCF).It adopts the Voltage Control Voltage Source(VCVS)equalized transfor-mation to revise the original LC ladder filter and induce it into 16 basic sections and then extend the princi-ple of the LT in order to fit active and 3 port networks and give out switched-capacitor circuits corre-sponding to the 16 basic sections,which can realize all four kinds of filters——LP,HP,BP,BS filters.De-signed examples are given here.An Nth order filter only requires N amplifiers and the circuit is insensitive toparasitic capacitances.The experimental results of a 3rd order elliptic LP and a 6th order elliptic BP are giv-en and agree with the theory.

A Novel Dual-Rate Sampling Switched-Capacitor Configuration and Its Application

In order to realize accurate bilinear transformation from s- to z-domain,a novelswitched-capacitor configuration is proposed in the light of principles of dual-rate sampling and chargeconservation,which has also been used for building a 5th-order elliptic lowpass filter.The filter issimulated and measured in typical 0.34 μm/3.3 V Si CMOS process models,special full differentialoperational amplifiers and CMOS transfer gate switches,which achieves 80 MHz sampling rate,17.8MHz cutoff frequency,0.052 dB maximum passband ripple,42.1 dB minimum stopband attenuation and74 mW quiescent power dissipation.At the same time,the dual-rate sampling topology breaks thetraditional restrictions of filter introduced by unit-gain bandwidth and slew rate of operational amplifiersand also improves effectively their performances in high-frequency applications.It has been applied forthe design of an anti-alias filter in analog front-end of video decoder IC with 15 MHz signal frequencyyet.

Multi-Phase QR ZCS Switched-Capacitor Bidirectional Power Converter for PV System Application

The multi-phase implementation in the QR （quasi resonant） ZCS （zero current switching） SC （switched capacitor） bidirectional DC-DC converter structure has been proposed to reduce current ripple, switching loss and significantly increase the converter efficiency and power density. This approach provides a more precise output voltage to obtain voltage conversion ratios from the double-mode versus half-mode to n-mode versus 1/n mode. This is accomplished by adding a different number of switched-capacitors and power MOSFET switches with a small series connected resonant inductor for forward and reverse schemes. The size and cost can be reduced when the proposed converter has been designed with the coupled inductors. The simulation and experimental results have been used to demonstrate the performance of the two-phase with and without coupled inductor interleaved QR ZCS SC converters for bidirectional power flow control application, and an extending structure for N-phase is mentioned.

Direct on Line Starting Induction Motor with Thyristor Switched Capacitor Based Voltage Regulation

The purpose of this paper is to show a laboratory scale implementation of a Thyristor Switched Capacitors （TSC） as an alternative for voltage regulation during a direct on line three-phase induction motor starting on an emulated weak transmission line. Thyristor switched capacitor bank was chosen because it is a well known topology, considering the very nature of the direct starting induction motors, which represents a highly inductive load, the use of switched reactors becomes unnecessary. Such fact minimizes the introduction of harmonics components, and also reduces the cost of the implementation. The binary disposition of the banks allows a variable Var compensation with sixteen steps, in this case. The solution makes use of low cost devices combined with sliding window voltage and current measurement algorithm and a PI control with dead band control for achieve the shown experimental results, where the system is able to manage a typically 20% voltage drop, reducing it to less than 4%. The schematic of the developed circuit, the control technique and a quite simple method to calculate the binary weight capacitors banks are also presented.

基于Switch-Capacitor网络实现分时供电的多输入升压变换器

在新能源联合发电系统中,多输入直流变换器可分时或同时向负载提供能量,具有简化系统结构、降低系统成本等优点。然而,现有的多输入直流变换器不能很好地满足新能源发电领域对高升压比、低纹波、低开关应力等技术参数的要求。因此,本文基于Switch-Capacitor网络串联放电、并联充电和多个网络累加升压的工作特性,推导出一种新型多输入升压变换器。本文以三输入升压变换器为例,详细分析了其在连续工作模式下的工作原理和工作性能,进行了仿真分析,并搭建了实验模型,仿真分析与实验研究的结果表明:①升压能力强,其升压比与Switch-Capacitor网络组中的网络个数有关;②开关器件的电压应力、输入电流纹波和输出电压纹波小;③所有开关管由同一控制信号隔离驱动,控制电路简单;④实现分时供电,元器件利用率高;⑤推演出对应的同时供电多输入升压变换器。

A General Method in the Synthesis of Ternary Double Pass-Transistor Circuits

A general method for designing ternary circuits using double pass-transistor logic is investigated. The logical relation of each MOS transistor is formulated by using the transmission operation in order to make effective and practical use of the circuits. A way to generate ternary complementary and dual circuits by applying the complementarity and duality principles is presented. This new static ternary double pass-transistor logic scheme has some favorable properties：the use of standard CMOS process without any modification of the thresholds, a perfectly symmetrical structure,a full logic swing, the maximum possible noise margins, a less complex structure, and no static power consumption. HSPICE simulations using TSMC 0.25μm CMOS technology and a 3V power supply demonstrate the effectiveness of the proposed design.

基于Switched-opamp的低功耗读出电路设计

利用开关运放技术对运放进行电源管理,实现了焦平面读出电路列运放的"休眠"-"唤醒"工作模式,使列运放仅在该列信号选通时工作。这种结构级功耗优化方法缩短了运放工作时间,降低了读出电路的功耗,适合低功耗系统应用要求。并设计了两种读出控制方案,对4×4元读出电路进行了瞬态分析。比照原有设计,该方法最多可以节省读出阶段列运放83%的功耗。

Composite Converter Combined APFC with Switched-capacitor Converter

To reduce switch numbers and voltage stress in semiconductor devices,this paper proposes a novel single-phase converter combined Active Power Factor Correction(APFC)with switched-capacitor converter.In addition,dynamic voltage regulation and voltage gain are improved by integrating the boost converter and switching capacitor cells.The interstage bulk capacitor is no longer needed.An average current control with redistribution of voltage in cells is proposed to obtain voltage lift ability of the switching capacitor cells and maintain a high-power factor.To study and verify the proposed converter preliminarily,theoretical analysis and simulation are presented in the paper.Furthermore,a 50o W prototype with two different configurations is built for experimental verification.The proposed converter can reach 95.62%of maximum efficiency,0.99 of power factor,and 3.55%of THD with 600 V output voltage,simultaneously.

The voltage-current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage-current relationships （VCRs） between two parallel memristive circuits - a parallel memristor and capacitor circuit （the parallel MC circuit）, and a parallel memristor and inductor circuit （the parallel ML circuit） - are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and exper/mental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results.

Simulation realization of skip cycle mode integrated control circuit in the switching power supply with low standby loss

This paper explores and proposes a design solution of an integrated skip cycle mode （SCM） control circuit with a simple structure. The design is simulated and implemented with XD10H-1.0μm modular DIMOS 650 V process. In order to meet the requirement of a wide temperature range and high yields of products, the schematic extracted from the layout is simulated with five process corners at 27℃ and 90℃. Simulation results demonstrate that the proposed integrated circuit is immune to noise and achieves skipping cycle control when switching mode power supply （SMPS） works with low load or without load.