An 18-bit sigma–delta switched-capacitor modulator using 4-order single-loop CIFB architecture

Oversampling sigma–delta(Σ–Δ)analog-to-digital converters(ADCs)are currently one of the most widely used architectures for high-resolution ADCs.The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed.Structurally,theΣ–ΔADC is divided into two parts:a front-end analog modulator and a back-end digital filter.The performance of the front-end analog modulator has a marked influence on the entireΣ–ΔADC system.In this paper,a 4-order single-loop switched-capacitor modulator with a CIFB(cascade-of-integrators feed-back)structure is proposed.Based on the chosen modulator architecture,the ASIC circuit is implemented using a chartered 0.35μm CMOS process with a chip area of 1.72×0.75 mm^2.The chip operates with a 3.3-V power supply and a power dissipation of 22 mW.According to the results,the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits(ENOB)was almost 18-bit.

NOVEL LINEAR TRANSFORMATION SWITCHED-CAPACITOR FILTER DESIGN

This paper presents a novel method that is applied to realize the Linear Transformation(LT)Switched-Capacitor Filter(SCF).It adopts the Voltage Control Voltage Source(VCVS)equalized transfor-mation to revise the original LC ladder filter and induce it into 16 basic sections and then extend the princi-ple of the LT in order to fit active and 3 port networks and give out switched-capacitor circuits corre-sponding to the 16 basic sections,which can realize all four kinds of filters——LP,HP,BP,BS filters.De-signed examples are given here.An Nth order filter only requires N amplifiers and the circuit is insensitive toparasitic capacitances.The experimental results of a 3rd order elliptic LP and a 6th order elliptic BP are giv-en and agree with the theory.

Design of Sixth-Order Lowpass Elliptic Switched-Capacitor Filter

In this paper the design and implementation of sixth-order lowpass elliptic switched-capacitor filter( SCF) for interface circuit of Micro-Electro-Mechanical System( MEMS) sensor are presented. This work aims to lower total harmonic distortion( THD) without deteriorating other performances. After system design in Simulink,the filter is realized in transistor level and finally fabricated in Central Semiconductor Manufacturing Corporation( CSMC) 0.5 μm metal-oxide-semiconductor( CMOS) technology. Typical measured results are: it operates with 25: 1 clock-to-corner frequency ratio and a 10 k Hz maximum corner frequency. The maximum passband ripple is about 0.49 d B and the minimum stopband rejection is 40 d B for the temperature from-20 ℃to 80 ℃. For the 250 k Hz clock frequency setting,given the 1 k Hz,- 8 d BVrms input signal,the measured worst case THD is-64 d B. The active area of the chip is 2.8 mm2 with 8 pads. The analog power dissipation is10 m W from a 5 V power supply.

Single-source Switched-capacitor Boost Nine-level Inverter with Reduced Components

Increasing demands for improvement in power quality and power capacity have contributed to development of switched-capacitor multilevel inverters(SCMLIs).Recently developed SCMLIs enable single-stage voltage boosting,as well as inversion resulting in step-up ac output.Towards reduction in number of components,this paper introduces a boost type singlesource nine-level(9-level)SCMLI employing two capacitors and three diodes.Owing to the series-parallel connection process,capacitor voltages are inherently balanced and assist in quadruple voltage boosting from a single-source.Maximum voltage stress across semiconductor devices is limited to twice input voltage only.Using a minimum number of components,the proposed SCMLI can be extended to increase voltage levels without additional dc input.Each extension module adds two additional voltage steps in the output while maintaining maximum voltage stress the same as 9-level circuit.Followed by in-depth analysis of circuit operation and power losses,a thorough comparison of recently developed single-phase 9-level MLIs is carried out,which verifies design superiority.Extensive simulation and experimental results are presented to verify the prominent features of the 9-level SCMLI under dynamic operating conditions.

A 150-nA 13.4-ppm/℃switched-capacitor CMOS sub-bandgap voltage reference

A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 035-μm 3.3-V/5-V dual gate mixed-signal CMOS process.The proposed circuit generates a precise sub-bandgap voltage of 1 V.The temperature coefficient of the output voltage is 13.4 ppm/℃with the temperature varying from -20 to 80℃.The proposed circuit operates properly with the supply voltage down to 1.3 V,and consumes 150 nA at room temperature.The line regulation is 0.27%/V.The power supply rejection ratio at 100 Hz and 1 MHz is -39 dB and -51 dB,respectively.The chip area is 0.2 mm2.

A Double Input-parallel-output-series Hybrid Switched-capacitor Boost Converter

A double input-parallel-output-series hybrid switched-capacitor boost(DIPOS-HSCB)converter is proposed which consists of two different kinds of input-parallel-output-series(IPOS)circuits,i.e.,inner IPOS circuit and outer IPOS circuit.Two boost modules and one switched-capacitor network build an inner IPOS circuit based IPOS-HSCB converter and two IPOS-HSCB converters develop the outer IPOS circuit based DIPOS-HSCB converter.With the proposed DIPOS-HSCB converter,a high voltage-gain with low component stress and small input current ripple are achieved.Furthermore,an automatic current balancing function for all input inductor currents can be also achieved using a special carrier phase-shifted modulation scheme.A prototype rated at 200 V/120 W has been developed and the maximum efficiency of the proposed DIPOS-HSCB converter is 95% at 120 W.Both steady and dynamic results are presented to validate the effectiveness of the proposed DIPOS-HSCB converter.

An offset-insensitive switched-capacitor bandgap reference with continuous output

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.

Low-power switched-capacitor delta-sigma modulator for EEG recording applications

This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram（EEG） monitoring applications.To reduce the power consumption,the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure.The modulator is designed in a 0.35-μm 2P4M standard CMOS process,with an active area of 365×290μm^2.Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio.The whole circuit consumes 515μW under a 2.5 V power supply,which is suitable for portable EEG monitoring.

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs

An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

A large-current, highly integrated switched-capacitor divider with a dual-branch interleaved topology and light load efficiency improvement

Because it is magnet-free and can achieve a high integration level,the switched-capacitor(SC)converter acting as a direct current transformer has many promising applications in modern electronics.However,designing an SC converter with large current capability and high power efficiency is still challenging.This paper proposes a dual-branch SC voltage divider and presents its integrated circuit(IC)implementation.The designed SC converter is capable of driving large current load,thus widening the use of SC converters to high-power applications.This SC converter has a constant conversion ratio of 1/2 and its dual-branch interleaved operation ensures a continuous input current.An effective on-chip gate-driving method using a capacitively coupled floating-voltage level shifter is proposed to drive the all-NMOS power train.Due to the self-powered structure,the flying capacitor itself is also a bootstrap capacitor for gate driving and thus reduces the number of needed components.A digital frequency modulation method is adopted and the switching frequency decreases automatically at light load to improve light load efficiency.The converter IC is implemented using a 180 nm triple-well BCD process.Experimental results verify the effectiveness of the dual-branch interleaved operation and the self-powered gate-driving method.The proposed SC divider can drive up to 4 A load current with 5–12 V input voltage and its power efficiency is as high as 96.5%.At light load,using the proposed optimization method,the power efficiency is improved by 30%.

Switched-capacitor Multi-level Inverter with Equal Distribution of the Capacitors Discharging Phases

A new switched-capacitor(2n+1)levels inverter with a single input source and equal charge of the capacitors at the input voltage V_(in) is presented.Compared with its peers from the same class of inverters,the proposed one features an equal or lower components count referred to the boost factor.And,it presents an additional advantage:each voltage level can be obtained by using different capacitors in the discharging phase,such that the decreasing part of the staircase output waveform can be synthesized with different switching topologies than those used in the increasing part.As a consequence,all the capacitors are discharged at the same voltage value at the end of each half-cycle,allowing for the use of smaller capacitors of equal values.When the capacitors are connected in parallel in the charging phase,there is no need to equalize their voltages,so no additional current spikes appear.This also implies less electromagnetic emission(EMI).Two types of modulation strategies are proposed.A half-height fundamental switching frequency modulation strategy allows for reaching the desired peak of the output voltage during the highest voltage level operation.It is advantageous in application of the inverter as a front end of a grid supplied by green sources of energy.A high frequency(f_(s)=200 kHz)modulation strategy accompanied by a duty-cycle control is advantageous for applications which require miniaturization.A 9-level switched-capacitor multi-level inverter(SCMLI)is analyzed and designed.The power losses are calculated.The experimental results for a 9-level inverter with V_(in)=40 V,V_(out)=110 Vrms 50 Hz,200 W confirm the theoretical expectations.

Switched-capacitor multiply-by-two amplifier with reduced capacitor mismatches sensitivity and full swing sample signal common-mode voltage

A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.

An 80-GHz DCO utilizing improved SC ladder and promoted DCTL-based hybrid tuning banks

An 80-GHz DCO based on modified hybrid tuning banks is introduced in this paper.To achieve sub-MHz frequency res-olution with reduced circuit complexity,the improved circuit topology replaces the conventional circuit topology with two binary-weighted SC cells,enabling eight SC-cell-based improved SC ladders to achieve the same fine-tuning steps as twelve SC-cell-based conventional SC ladders.To achieve lower phase noise and smaller chip size,the promoted binary-weighted digi-tally controlled transmission lines(DCTLs)are used to implement the coarse and medium tuning banks of the DCO.Compared to the conventional thermometer-coded DCTLs,control bits of the proposed DCTLs are reduced from 30 to 8,and the total length is reduced by 34.3%(from 122.76 to 80.66μm).Fabricated in 40-nm CMOS,the DCO demonstrated in this work fea-tures a small fine-tuning step(483 kHz),a high oscillation frequency(79-85 GHz),and a smaller chip size(0.017 mm^(2)).Com-pared to previous work,the modified DCO exhibits an excellent figure of merit with an area(FoMA)of-198 dBc/Hz.

Noise analysis and characterization of a full differential CMOS interface circuit for capacitive closed-loop micro-accelerometer

To achieve a high precision capacitive closed-loop micro-accelerometer,a full differential CMOS based on switched-capacitor circuit was presented in this paper as the sensor interface circuit.This circuit consists of a balance-bridge module,a charge sensitive amplifier,a correlated-double-sampling module,and a logic timing control module.A special two-path feedback circuit configuration was given to improve the system linearity.The quantitative analysis of error voltage and noise shows that there is tradeoff around circuit's noise,speed and accuracy.A detailed design method was given for this tradeoff.The noise performance optimized circuit has a noise root spectral density of 1.0 μV/Hz,equivalent to rms noise root spectral density of 1.63 μg/Hz.Therefore,the sensor's Brown noise becomes the main noise source in this design.This circuit is designed with 0.5 μm n-well CMOS process.Under a ±5 V supply,the Hspice simulation shows that the system sensitivity achieves 0.616 V/g,the system offset is as low as 1.456 mV,the non-linearity is below 0.03%,and the system linear range achieves ±5 g.

PARASITIC TOLERANT DIFFERENTIAL SC TRANSCONDUCTANCE USING UNITY GAIN BUFFERS

The unity gain buffer will be good to design high frequency SCF if its resistiveeffects can be eliminated,and therefore the whole parasitic sensitivities will greatly be reduced.On the basis of this concept,a novel parasitic tolerant SC DTE(differential transconductanceelement)is proposed.SC floating inductor and integrator fit for high frequency applications areformed by the DTE.The computer simulation and experiment on a third order elliptic LP filterverify its validity.

HIGH SELECTIVITY SC BANDPASS FILTERS WITH LESS CAPACITOR SPREAD

Two novel switched-capacitor(SC)bandpass filters using a single operational am-plifier(op amp)are presented.Optimal designs for minimizing capacitor spread are also given.Gain-bandwidth product(GB)effects of op amps on the proposed SC circuits are taken intoconsideration.Comparisons with the proposed circuits and the circuits given by the literatureshow that the new circuits require less chip area in monolithic integration and are less sensitiveto the GB effects.

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

This paper presents the design of a two-stage bulk-input pseudo-differential operational transconductance amplifier (OTA) and its application in active-RC filters. The OTA was designed in 90 nm CMOS process and operates at a single supply voltage of 0.5 V. Using a two-path bulk-driven OTA by the combination of two different amplifiers the DC gain and speed of the OTA is increased. Rail-to-rail input is made possible using the transistor’s bulk terminal as in input. Also a Miller-Feed-forward (MFF) compensation is utilized which is improved the gain bandwidth (GBW) and phase margin of the OTA. In addition, a new merged cross-coupled self-cascode pair is used that can provide higher gain. Also, a novel cost-effective bulk-input common-mode feedback (CMFB) circuit has been designed. Simplicity and ability of using this new merged CMFB circuit is superior compared with state-of-the-art CMFBs. The OTA has a 70.2 dB DC gain, a 2.5 MHz GBW and a 70.8o phase margin for a 20 PF capacitive load whereas consumes only 25 μw. Finally, an 8th order Butterworth active Biquadrate RC filter has been designed and this OTA was checked by a typical switched-capacitor (SC) integrator with a 1 MHz clock-frequency.

A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation

A 2.4 GHz high-linearity low-phase-noise cross-coupled CMOS LC voltage-controlled oscillator（VCO） is implemented in standard 0.18-μm CMOS technology.An equalization structure for tuning sensitivity base on the three-stage distributed biased switched-varactor bank and the differential switched-capacitor bank is adopted to reduce the variations of the VCO gain,achieve high linearity,and optimize the phase-noise performance.Compared to the conventional VCO,the proposed VCO has more constant gain over the entire tuning range.The tuning range is about 18.7%from 2.23 to 2.69 GHz,and the phase noise is-95 dBc/Hz at 100-kHz offset and-117 dBc/Hz at 1-MHz offset from the carrier frequency of 2.42 GHz.The power dissipation is 2.1 mW from a 1.8 V power supply.The active area of this VCO is 500×810μm^2.

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.

An 18-bit high performance audio ∑-△D/A converter

A multi-bit quantized high performance sigma-delta（Σ-Δ） audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average（DWA） mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm^2.The measured dynamic range（DR） and peak SNDR are 96 dB and 88 dB,respectively.