Stability analysis of linear/nonlinear switching active disturbance rejection control based MIMO continuous systems

In this paper,a linear/nonlinear switching active disturbance rejection control(SADRC)based decoupling control approach is proposed to deal with some difficult control problems in a class of multi-input multi-output(MIMO)systems such as multi-variables,disturbances,and coupling,etc.Firstly,the structure and parameter tuning method of SADRC is introduced into this paper.Followed on this,virtual control variables are adopted into the MIMO systems,making the systems decoupled.Then the SADRC controller is designed for every subsystem.After this,a stability analyzed method via the Lyapunov function is proposed for the whole system.Finally,some simulations are presented to demonstrate the anti-disturbance and robustness of SADRC,and results show SADRC has a potential applications in engineering practice.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

An LFSR-based address generator using optimized address partition for low power memory BIST

Power consumption in test mode is much higher than that in normal mode,which is prone to causing circuit damage and reducing the yield of chips.To reduce the power dissipation efficiently,a modified linear feedback shift register(LFSR)is designed to decrease switching activity dramatically during the generation of address sequences for memory built-in self-test(MBIST).The address models are generated by a blend of two address generators with an optimized address partition and two distinct controlled clock signals.An address generator circuit for MBIST of 64 k×32 static random access memory(SRAM)is designed to illustrate the proposed scheme.Experimental results show that when the address bus size is 16 bits,compared with the traditional LFSR,the proposed LFSR can reduce the switching activity and dynamic power by 71.1%and 68.2%,respectively,with low area overhead.

Power-optimal encoding for low-power address bus

This paper presented a novel bus encoding method to reduce the switching activity on address buses and hence reduce power dissipation. Dynamic-sorting encoding(DSE) method reduces the power dissipation of address bus based on the dynamic reordering of the modified offset address bus lines. This method reorders the ten least significant bits of offset address according to the range of offset address, and the optimal sorting pattern is transmitted through the high bits of address bus without the need for redundant bus lines. The experimental results by using an instruction set simulator and SPEC2000 benchmarks show that DSE method can reduce signal transitions on the address bus by 88.2%, and the actual overhead of the encoder circuit is estimated after encoder is designed and synthesized in 0.18-μm CMOS technology. The results show that DSE method outperforms the low-power encoding schemes presented in the past.

Pyrophosphate-Mediated On-Off-On Oxidase-Like Activity Switching of Nanosized MnFe_(2)O_(4) for Alkaline Phosphatase Sensing

Developing reliable and facile approaches for alkaline phosphatase(ALP)sensing is important due to its role as a clinical biomarker for many diseases.In this study,we proposed a new and convenient colorimetric assay based on the pyrophosphate(PPi)-mediated oxidase-mimicking activity switching of nanosized MnFe_(2)O_(4) for the detection of ALP.The synthesized MnFe_(2)O_(4) exhibited high oxidase-like activity to catalyze the oxidation of colorless 3,3′,5,5′-tetramethylbenzidine(TMB)to its blue product TMBox in the presence of dissolved O2,leading to a color reaction rapidly and remarkably;PPi could significantly inhibit the activity of the MnFe_(2)O_(4) nanozyme via the strong interaction between PPi and the Fe(III)species in MnFe_(2)O_(4),resulting in the suppression of the TMB color reaction;when ALP was added,it hydrolyzed the PPi substrate to phosphate(Pi)that had no obvious effect on the MnFe_(2)O_(4) activity,and such that the TMB color reaction catalyzed by the nanozyme could be observed again.With the above principle,linear colorimetric determination of ALP in the scope of 0.6-55 U L−1 was achieved,giving the limit of detection down to 0.27 U L−1.Besides,the developed assay could provide selective response toward ALP against other co-existing biological species.Furthermore,reliable detection of ALP in human serum samples was verified by our assay,revealing its great promise as an effective and facile tool for ALP monitoring in clinical practice.

Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization

Finite state machine （FSM） plays a vital current which is drawn by state transitions can result in role in the sequential logic design. In an FSM, the high peak large voltage drop and electromigration which significantly affect circuit reliability. Several published papers show that the peak current can be reduced by post-optimization schemes or Boolean satisfiability （SAT）-based formulations. However, those methods of reducing the peak current either increase the overall power dissipation or are not efficient. This paper has proposed a low power state assignment algorithm with upper bound peak current constraints. First the peak current constraints are weighted into the objective function by Lagrangian relaxation technique with Lagrangian multipliers to penalize the violation. Second, Lagrangian sub-problems are solved by a genetic algorithm with Lagrangian multipliers updated by the subgradient optimization method. Finally, a heuristic algorithm determines the upper bound of the peak current, and achieves optimization between peak current and switching power. Experimental results of International Workshop on Logic and Synthesis （IWLS） 1993 benchmark suites show that the proposed method can achieve up to 45.27% reduction of peak current, 6.31% reduction of switching power, and significant reduction of run time compared with previously published results.

Goal-Based Automated Code Generation in Self-Adaptive System

System administrator deals with many problems,as computing environment becomes increasingly complex.Systems with an ability to recognize system states and adapt to resolve these problems offer a solution.Much experience and knowledge are required to build a self-adaptive system.Self-adaptive systems have inherent difficulties.This paper proposes a technique that automatically generates the code for the self-adaptive system.Thus the system is easier to build.Self-adaptive systems of previous research required high system resource usage.Incorrect operation could be invoked by external factors such as viruses.We propose an improved self-adaptive system approach and apply it to video conference system and robot system.We compared the lines of code,the number of classes created by the developers.We have confirmed this enhanced approach to be effective in reducing these development metrics.

A High-Speed Active Switch Routing Architecture

In this paper, combining with active networks, we design a new kind of programmable routing switch architecture to provide a common intelligent switch platform for multi-protocol switching and multi-service accessing. We elaborate how programmable switch and network intelligence are achieved, and how packets are classified, queued and scheduled. We point out that edge intelligence and network software are the tendency for the development of future networks.

Actively controllable terahertz switches with graphene-based nongroove gratings

We systematically investigated the tunable dynamic characteristics of a broadband surface plasmon polariton(SPP) wave on a silicon-graded grating structure in the range of 10–40 THz with the aid of single-layer graphene.The theoretical and numerical simulated results demonstrate that the SPPs at different frequencies within a broadband range can be trapped at different positions on the graphene surface, which can be used as a broadband spectrometer and optical switch. Meanwhile, the group velocity of the SPPs can be modulated to be several hundred times smaller than light velocity in vacuum. Based on the theoretical analyses, we have predicted the trapping positions and corresponding group velocities of the SPP waves with different frequencies. By appropriately tuning the gate voltages, the trapped SPP waves can be released to propagate along the surface of graphene or out of the graded grating zone. Thus, we have also investigated the switching characteristics of the slow light system, where the optical switching can be controlled as an "off" or "on" mode by actively adjusting the gate voltage. The slow light system offers advantages, including broadband operation, ultracompact footprint, and tunable ability simultaneously, which holds great promise for applications in optical switches.