Multi-layer phenomena in petawatt laser-driven acceleration of heavy ions

Laser-accelerated high-flux-intensity heavy-ion beams are important for new types of accelerators.A particle-in-cell program(Smilei) is employed to simulate the entire process of Station of Extreme Light(SEL) 100 PW laser-accelerated heavy particles using different nanoscale short targets with a thickness of 100 nm Cr, Fe, Ag, Ta, Au, Pb, Th and U, as well as 200 nm thick Al and Ca. An obvious stratification is observed in the simulation. The layering phenomenon is a hybrid acceleration mechanism reflecting target normal sheath acceleration and radiation pressure acceleration, and this phenomenon is understood from the simulated energy spectrum,ionization and spatial electric field distribution. According to the stratification, it is suggested that high-quality heavy-ion beams could be expected for fusion reactions to synthesize superheavy nuclei. Two plasma clusters in the stratification are observed simultaneously, which suggest new techniques for plasma experiments as well as thinner metal targets in the precision machining process.

基于综合健康指数与RVM的系统级失效预测

针对具有多维状态变量、多种工作模式和故障模式的复杂工程系统,提出一种基于综合健康指数(synthesized health index,SHI)与相关向量机(relevance vector machine,RVM)的系统级失效预测方法。在离线训练阶段,先根据有限失效历史数据建立各工作模式下的健康评估模型,并据此获得各历史退化轨迹的SHI序列;然后再使用RVM对这些序列进行回归处理,进而辨识出与回归曲线最为匹配的函数模型。在线预测阶段,先运用健康评估模型计算当前设备的SHI序列并进行RVM回归,再拟合出离线阶段确定的函数模型并添加时变噪声;最后,外推预测出系统剩余使用寿命的概率密度分布。该方法成功应用到涡轮发动机的失效预测案例。

Synthes线缆系统置入内固定治疗全髋关节置换后股骨假体周围骨折

背景:近年来股骨假体周围骨折已经成为是全髋关节置换后最常见的并发症之一,Vancourver B1型骨折因为股骨柄假体稳定同时无明显骨缺损,目前多主张积极行内固定治疗。目的:探讨Synthes线缆系统置入内固定治疗全髋关节置换后Vancouver B1型股骨假体周围骨折的临床效果。方法:2009年5月至2012年10月南通市第一人民医院骨科采用Synthes线缆系统置入内固定治疗18例全髋关节置换后Vancouver B1型股骨假体周围骨折患者,女10例,男8例;年龄45-80岁,平均(62.67±8.67)岁。治疗后第1,3,6个月复诊,按Harris评分标准评定髋关节功能,满分为100分,≥90分为优,80-89分为较好,70-79分为良,<70分为差。结果与结论:18例患者均获得随访,18例获得随访6-43个月,患者平均骨折愈合时间为(19.06±4.04)周。18例治疗前Harris评分为(22.3±3.6)分,治疗后第1,3,6个月髋关节Harris评分均较治疗前显著提高(P<0.01),髋关节功能恢复良好。提示Synthes线缆系统能最大程度恢复股骨正常解剖结构,操作简便,损伤小,稳定性强,安全性高,是治疗Vancouver B1型股骨假体周围骨折的理想方法。

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A CMOS Fully Integrated Frequency Synthesizer with Stability Compensation

A complete closed-loop third order s-domain model is analyzed for a frequency synthesizer. Based on the model and root-locus technique, the procedure for parameters design is described, and the relationship between the process,voltage,and temperature variation of parameters and the loop stability is quantitatively analyzed. A variation margin is proposed for stability compensation. Furthermore,a simple adjustable current cell in the charge pump is proposed for additional stability compensation and a novel VCO with linear gain is adopted to limit the total variation. A fully integrated frequency synthesizer from 1 to 1.05GHz with 250kHz channel resolution is implemented to verify the methods.

A New High Performance FM Transmitter

A new FM transmitter is reported. It adopts a fractional-N PLL synthesizer to realize the FM modulator. An extra offset current has also been applied to eliminate the effects of the mismatch in CP. The chip is fabricated with CSMC 0.5μm DPTM CMOS technology. Experiments show that it achieves THD≤0.08% and SNR≤ 82dB,and the maximum outband emission energy ≤ 90dBc/Hz. Furthermore,it also uses an auto frequency adjusting method to avoid tuning up the external inductances. All these merits are very suitable for FM transmission.

A new method to construct reservoir capillary pressure curves using NMR log data and its application

By analyzing hundreds of capillary pressure curves, the controlling factors of shape and type of capillary pressure curves are found and a novel method is presented to construct capillary pressure curves by using reservoir permeability and a synthesized index. The accuracy of this new method is verified by mercury-injection experiments. Considering the limited quantity of capillary pressure data, a new method is developed to extract the Swanson parameter from the NMR T2 distribution and estimate reservoir permeability. Integrating with NMR total porosity, reservoir capillary pressure curves can be constructed to evaluate reservoir pore structure in the intervals with NMR log data. An in-situ example of evaluating reservoir pore structure using the capillary pressure curves by this new method is presented. The result shows that it accurately detects the change in reservoir pore structure as a function of depth.

Low Jitter,Dual-Modulus Prescalers for RF Receivers

Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

A Novel 4/5 Prescaler with Automatic Power Down

An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mixed-sig- nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique. The simulation results show that the new 4/5 prescaler is immune to the ＂wake-up＂ issue and thereby retains the same maxi- mum operating frequency as the conventional prescaler. An integer-N divider with this proposed prescaler and with the di- vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

某些钴(Ⅲ)氨基酸络合物的活性炭催化合成

在研究光学活性络合物的手性识别及拆分机理的过程中,需要合成一系列有特征构型的光学活性钻（Ⅲ）络合物,其配体皆为含N、O配位原子的多齿配体。但是按文献方法合成具有光学活性的u-fac-[Co（ida）2]（ida2;亚氨基二乙酸根）、fac-[Co（β-ala）3]（β-ala:β-丙氨酸根）时,均存在着产率低或产物纯度低,反应时间长等问题,为其后续拆分带来不少困难。为此。

Survey of Radiosensitizing Agents (Synthesized Chemicals and Gene Therapeutic Agents) Since 2000

Radiotherapy has played an important role in treatment of tumor patientssince it appeared about 80 years ago, and has been an indispensable part of the management of about50% of tumors (especially 60% - 70% of malignant tumors). Currently, radiotherapy is used in simpleand palliative therapy, adjuvant therapy after or before surgery, simultaneous radio-chemotherapy,combined BRM (biological response modifier) therapy, ets. Radiosensitizing agents enhance theradiation effects on tumor cells so as to have better responses in radiotherapy. Tumor intrinsicradiosensitivity is affected by the hy-poxic level in solid tumor, the ability of the cells torepair the radiation-induced DNA damage, the number of cells which have a clonogenic capability toreestablish uncontrolled cell growth, the amount of dividing cells, and the distribution of cellsthroughout the cell cycle. Consequently , it is necessary and useful to add one or moreradiosensitizing agents in radiotherapy to increase the radio-sensitivity of tumor cells.

微弱信号检测与锁定放大电路

介绍了一种微弱信号的检测与锁定放大方法。通过模拟锁相环工作锁定待检微弱信号的频率,利用控制器测量该锁相环的输出频率,并根据该频率值控制直接数字合成电路产生同频信号,该信号作为相关检测所需的参考信号。系统采用乘法器和积分电路实现相关检测,通过步进调整参考信号的相位,使互相关值最大,获得与被测信号同频同相的再生信号,从而实现微弱信号的检测与放大。该方法能够实现频率检测及幅度检测等功能。经实验测试表明:在低信噪比条件下,该方法仍具有较好的线性测量特性和较高的准确度,可实现任意波形的微弱信号自动检测和再生放大。

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

A novel method to partially compensate sigma-delta shaped noise is proposed. By injecting the compensation current into the passive loop filter during the delay time of the phase frequency detector（PFD）,a maximum reduction of the phase noise by about 16dB can be achieved. Compared to other compensation methods,the technique proposed here is relatively simple and easy to implement. Key building blocks for realizing the noise cancellation,including the delay variable PFD and compensation current source, are specially designed. Both the behavior level and circuit level simulation results are presented.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.