In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant...In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..展开更多
With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a C...With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.展开更多
Usually a single MPEG2 video encoder chip realizes the multiple post stage tasks of motion estimation, such as motion vector refinement and prediction error generation, using multiple hardware modules. This paper p...Usually a single MPEG2 video encoder chip realizes the multiple post stage tasks of motion estimation, such as motion vector refinement and prediction error generation, using multiple hardware modules. This paper proposes a new architecture using only a single module to implement the post stage tasks of motion estimation, which has a single instruction stream over multiple data streams (SIMD). The new architecture is simple and more regular; capable of providing sufficient computational power and of adapting to the encoding flexibility required by the MPEG2 standard. Therefore, it is a more suitable architecture for the system on a chip. NEL Corporation (NTT Electronics, Japan) has integrated a circuit based on this architecture into the single MPEG2 MP@ML encoder chip, which uses the multiresolution telescopic search motion estimation algorithm. Using 0.25 μm CMOS, four metal layer technology, this circuit has 15.4 M gates with an area of about 29 mm 2. The operating clock frequency is 81 MHz.展开更多
文摘In order to improve the system reliability and performance and to reduce the system cost, volume and weight, we have designed, fabricated and tested the multibus adapter system of a trimodular redundant fault tolerant computer system on a single chip of 5000 gate CMOS gate array. The design, fabrication and test of this single chip system will be discussed..
基金funded by the "333 Engineering" Assistance Project of Jiangsu Province,China (No. BRA2011115)
文摘With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.
文摘Usually a single MPEG2 video encoder chip realizes the multiple post stage tasks of motion estimation, such as motion vector refinement and prediction error generation, using multiple hardware modules. This paper proposes a new architecture using only a single module to implement the post stage tasks of motion estimation, which has a single instruction stream over multiple data streams (SIMD). The new architecture is simple and more regular; capable of providing sufficient computational power and of adapting to the encoding flexibility required by the MPEG2 standard. Therefore, it is a more suitable architecture for the system on a chip. NEL Corporation (NTT Electronics, Japan) has integrated a circuit based on this architecture into the single MPEG2 MP@ML encoder chip, which uses the multiresolution telescopic search motion estimation algorithm. Using 0.25 μm CMOS, four metal layer technology, this circuit has 15.4 M gates with an area of about 29 mm 2. The operating clock frequency is 81 MHz.
