For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchron...For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.展开更多
The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling...The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling goal and constraint character,a heuristics rule-based multi-stage link scheduling algorithm was put forward.The algorithm distinguishes the on-off-frontier satellites from the others and schedules them by turns.The paper presented the main flow as well as the detailed design of the rule.Finally based on the current COMPASS global system,some typical resources and constraints are selected to generate an instance.Then the comparison analysis between the heuristics scheduling algorithm and three other traditional scheduling strategies are carried out.The result shows the validity and reasonability of the multi-stage strategy.展开更多
Satellite disciplined clock system(SDCS)composed of satellite timing receiver and local frequency synthesis is widely applied for its high accuracy and low cost.This paper provides a review of SDCS.Key technologies su...Satellite disciplined clock system(SDCS)composed of satellite timing receiver and local frequency synthesis is widely applied for its high accuracy and low cost.This paper provides a review of SDCS.Key technologies such as phase difference measurement,pulse noise process and frequency calibration are surveyed in detail.Disciplined clock model based on PI controller is built and disciplined process is analyzed.The methods of realizing the disciplined clock circuit are classified and summarized.A prototype based on FPGA is proposed.At last development trend of SDCS is discussed.展开更多
The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a ses...The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a session layer,for message scheduling,to the existing CAN standard,which is a two layer standard comprising of a physical layer and a data link layer. TTCAN facilitates network communication in a time-triggered fashion,by introducing a Time Division Multiple Access style communication scheme. This allows deterministic network behavior,where maximum message latency times can be quantified and guaranteed. In order to solve the problem of determinate time latency and synchronization among several districted units in one auto panel CAN systems,this paper proposed a prototype design implementation for a shared-clock scheduler based on PIC18F458 MCU. This leads to improved CAN system performance and avoid the latency jitters and guarantee a deterministic communication pattern on the bus. The real runtime performance is satisfied.展开更多
基金Supported by the National Natural Science Foundation of China(No.11005107)Anhui University Natural Science Research(No.K J2010A334)
文摘For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.
基金National Natural Science Foundations of China(Nos.71201171,71501179)
文摘The execution process of satellite-ground clock synchronization and ephemeris uploading in the system is analyzed,as well as their characterized operation and their relationship.Based on the analysis of the scheduling goal and constraint character,a heuristics rule-based multi-stage link scheduling algorithm was put forward.The algorithm distinguishes the on-off-frontier satellites from the others and schedules them by turns.The paper presented the main flow as well as the detailed design of the rule.Finally based on the current COMPASS global system,some typical resources and constraints are selected to generate an instance.Then the comparison analysis between the heuristics scheduling algorithm and three other traditional scheduling strategies are carried out.The result shows the validity and reasonability of the multi-stage strategy.
文摘Satellite disciplined clock system(SDCS)composed of satellite timing receiver and local frequency synthesis is widely applied for its high accuracy and low cost.This paper provides a review of SDCS.Key technologies such as phase difference measurement,pulse noise process and frequency calibration are surveyed in detail.Disciplined clock model based on PI controller is built and disciplined process is analyzed.The methods of realizing the disciplined clock circuit are classified and summarized.A prototype based on FPGA is proposed.At last development trend of SDCS is discussed.
文摘The Controller Area Network (CAN) is a well established control network for automotive and automation control applications. Time-Triggered Controller Area Network (TTCAN) is a recent development which introduces a session layer,for message scheduling,to the existing CAN standard,which is a two layer standard comprising of a physical layer and a data link layer. TTCAN facilitates network communication in a time-triggered fashion,by introducing a Time Division Multiple Access style communication scheme. This allows deterministic network behavior,where maximum message latency times can be quantified and guaranteed. In order to solve the problem of determinate time latency and synchronization among several districted units in one auto panel CAN systems,this paper proposed a prototype design implementation for a shared-clock scheduler based on PIC18F458 MCU. This leads to improved CAN system performance and avoid the latency jitters and guarantee a deterministic communication pattern on the bus. The real runtime performance is satisfied.
