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Novel Asynchronous Wrapper and Its Application to GALS Systems
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作者 庄圣贤 彭安金 Lars Wanhammar 《Journal of Southwest Jiaotong University(English Edition)》 2006年第1期34-40,共7页
An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a loca... An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Mttller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology. 展开更多
关键词 GALS Asynchronous wrapper Handshake circuit systems-on-chip (SoC)
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CADSE: communication aware design space exploration for efficient run-time MPSoC management
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作者 Amit Kumar SINGH Akash KUMAR +1 位作者 Jigang WU Thambipillai SRIKANTHAN 《Frontiers of Computer Science》 SCIE EI CSCD 2013年第3期416-430,共15页
Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip (MPSoC). Tasks of the applications need to be mapped on the MPSoC resources efficiently i... Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip (MPSoC). Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisity their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources' status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration (CADSE) techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results. 展开更多
关键词 multiprocessor systems-on-chip design space exploration run-time mapping synchronous dataflow graphs THROUGHPUT
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