Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation

Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.

A novel GAAC FinFET transistor:device analysis, 3D TCAD simulation, and fabrication

We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.

Simulation of Gate-All-Around Cylindrical Transistors for Sub-10 Nanometer Scaling

A gate-all-around cylindrical （GAAC） transistor for sub-10nm scaling is proposed. The GAAC transistor device physics,TCAD simulation,and proposed fabrication procedure are reported for the first time. Among all other novel FinFET devices, the gate-all-around cylindrical device can be particularly applied for reducing the problems of the conventional multi-gate FinFET and improving the device performance and the scale down capability. According to our simulation,the gate-all-around cylindrical device shows many benefits over conventional multi-gate FinFET, including gate-all- around rectangular （GAAR） devices. With gate-all-around cylindrical architecture,the transistor is controlled by an essen- tially infinite number of gates surrounding the entire cylinder-shaped channel. The electrical integrity within the channel is improved by reducing the leakage current due to the non-symmetrical field accumulation such as the corner effect. The proposed fabrication procedures for devices having GAAC device architecture are also discussed. The method is characterized by its simplicity and full compatibility with conventional planar CMOS technology.

Simulation of MoS_(2)stacked nanosheet field effect transistor

Transition metal dichalcogenides are nowadays appealing to researchers for their excellent electronic properties.Vertical stacked nanosheet FET(NSFET)based on MoS_(2)are proposed and studied by Poisson equation solver coupled with semiclassical quantum correction model implemented in Sentaurus workbench.It is found that,the 2D stacked NSFET can largely suppress short channel effects with improved subthreshold swing and drain induced barrier lowering,due to the excellent electrostatics of 2D MoS_(2).In addition,small-signal capacitance is extracted and analyzed.The MoS_(2)based NSFET shows great potential to enable next generation electronics.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors(SiGe HBTs)can change with decreasing temperature from+20℃to-180℃.This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform.Firstly,when the temperature drops from+20℃to-140℃,the increased carrier mobility drives a slight increase in transient amplitude.However,as the temperature decreases further below-140℃,the carrier freeze-out brings about an inflection point,which means the transient amplitude will decrease at cryogenic temperatures.To better understand this result,we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt's new incomplete ionization model.The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional(2D)TCAD process simulation.In addition,we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions.The increase of the emitter-base junction's barrier height at low temperatures could suppress this electron-injection phenomenon.We have also optimized the built-in voltage equations of a high current compact model(HICUM)by introducing the impact of incomplete ionization.The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures,and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

Synergistic effect of total ionizing dose on single-event gate rupture in SiC power MOSFETs

The synergistic effect of total ionizing dose(TID) and single event gate rupture(SEGR) in SiC power metal–oxide–semiconductor field effect transistors(MOSFETs) is investigated via simulation. The device is found to be more sensitive to SEGR with TID increasing, especially at higher temperature. The microscopic mechanism is revealed to be the increased trapped charges induced by TID and subsequent enhancement of electric field intensity inside the oxide layer.

Scaling effects of single-event gate rupture in thin oxides

The dynamics of the excess carriers generated by incident heavy ions are considered in both SiO2 and Si substrate. Influences of the initial radius of the charge track, surface potential decrease, external electric field, and the LET value of the incident ion on internal electric field buildup are analyzed separately. Considering the mechanisms of recombination, impact ionization, and bandgap tunneling, models are verified by using published experimental data. Moreover, the scaling effects of single-event gate rupture in thin gate oxides are studied, with the feature size of the MOS device down to 90 nm. The walue of the total electric field decreases rapidly along with the decrease of oxide thickness in the first period （1 2 nm to 3.3 nm）, and then increases a little when the gate oxide becomes thinner and thinner （3.3 nm to 1.8 nm）.

Device topological thermal management of β-Ga_(2)O_(3) Schottky barrier diodes

The ultra-wide bandgap semiconductor β gallium oxide(β-Ga_(2) O_(3)) gives promise to low conduction loss and high power for electronic devices. However, due to the natural poor thermal conductivity of β-Ga_(2) O_(3), their power devices suffer from serious self-heating effect. To overcome this problem, we emphasize on the effect of device structure on peak temperature in β-Ga_(2) O_(3) Schottky barrier diodes(SBDs) using TCAD simulation and experiment. The SBD topologies including crystal orientation of β-Ga_(2) O_(3), work function of Schottky metal, anode area, and thickness, were simulated in TCAD, showing that the thickness of β-Ga_(2) O_(3) plays a key role in reducing the peak temperature of diodes. Hence, we fabricated β-Ga_(2) O_(3) SBDs with three different thickness epitaxial layers and five different thickness substrates. The surface temperature of the diodes was measured using an infrared thermal imaging camera. The experimental results are consistent with the simulation results. Thus, our results provide a new thermal management strategy for high power β-Ga_(2) O_(3) diode.

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.

Impact of neutron-induced displacement damage on the single event latchup sensitivity of bulk CMOS SRAM

Since the displacement damage induced by the neutron irradiation prior has negligible impact on the performance of the bulk CMOS SRAM, we use the neutron irradiation to degrade the minority carrier lifetime in the regions responsible for latchup. With the experimental results, we discuss the impact of the neutron-induced displacement damage on the SEL sensitivity and qualitative analyze the effectiveness of this suppression approach with TCAD simulation.

An insulated-gate bipolar transistor model based on the finite-volume charge method

A finite-volume charge method has been proposed to simulate PIN diodes and insulated-gate bipolar transistor(IGBT)devices using SPICE simulators by extending the lumped-charge method.The new method assumes local quasi-neutrality in the undepleted N^(-)base region and uses the total collector current,the nodal hole density and voltage as the basic quantities.In SPICE implementation,it makes clear and accurate definitions of three kinds of nodes—the carrier density nodes,the voltage nodes and the current generator nodes—in the undepleted N^(-)base region.It uses central finite difference to approximate electron and hole current generators and sets up the current continuity equation in a control volume for every carrier density node in the undepleted N^(-)base region.It is easy to increase the number of nodes to describe the fast spatially varying carrier density in transient processes.We use this method to simulate IGBT devices in SPICE simulators and get a good agreement with technology computer-aided design simulations.

Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional(3 D)TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor(NMOS)transistor or P-channel metal-oxide semiconductor(PMOS)transistor can mitigate the cross section of single event upset(SEU)in 14-nm complementary metal-oxide semiconductor(CMOS)bulk Fin FET technology.The competition of charge collection between well boundary and sensitive nodes,the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section.Unlike dualinterlock cell(DICE)design,this approach is more effective under heavy ion irradiation of higher LET,in the presence of enough taps to ensure the rapid recovery of well potential.Besides,the feasibility of this method and its effectiveness with feature size scaling down are discussed.

Silicon cross-coupled gated tunneling diodes

Tunneling-based static random-access memory(SRAM)devices have been developed to fulfill the demands of high density and low power,and the performance of SRAMs has also been greatly promoted.However,for a long time,there has not been a silicon based tunneling device with both high peak valley current ratio(PVCR)and practicality,which remains a gap to be filled.Based on the existing work,the current manuscript proposed the concept of a new silicon-based tunneling device,i.e.,the silicon crosscoupled gated tunneling diode(Si XTD),which is quite simple in structure and almost completely compatible with mainstream technology.With technology computer aided design(TCAD)simulations,it has been validated that this type of device not only exhibits significant negative-differential-resistance(NDR)behavior with PVCRs up to 10^(6),but also possesses reasonable process margins.Moreover,SPICE simulation showed the great potential of such devices to achieve ultralow-power tunneling-based SRAMs with standby power down to 10^(−12)W.

Single event transient characterization of SiGe HBT by SPA experiment and 3-D process simulation

The single-photon absorption induced single event transient in the silicon-germanium heterojunction bipolar transistor is investigated.The laser wavelength and bias condition have been proven to have significant impacts on the characterization of the single event transient(SET) response of the device by two-dimensional(2-D) raster scanning.After optical analytical calculation,the laser-induced charge distribution is well-embedded in the 3-D TCAD process simulation conducted to explore the underlying physical mechanism.In addition to the ion shunt effect,the excess electron injection from the emitter to the base could play a vital role in the SET peak amplitude and charge collection.The impact of the metal layer on the SPA experimental results is also determined by establishing a figure of merit that will help researchers estimate the laser-induced transient sensitivity of devices with metal layer blocking.

A simulation analysis of performance of both implanted doping and in situ doping ETSOI PMOSFETs

Extremely thin silicon on insulator p-channel metal oxide-semiconductor field-effect transistors （PMOSFETs） with implanted doping and in situ doping are analyzed by TCAD simulation. The critical characteris- tic parameters acquired by TCAD simulation are compared with each other to analyze their electrical perfbrmance. The saturated driven currents of implanted doping devices with a 25 nm gate length （Lg） are about 200 ×μA/μm bigger than the in situ doping devices at the same saturated threshold voltage （Vtsat）. Meanwhile the drain-induced barrier lowering （DIBL） and saturated subthreshold swings for implanted doping devices are also 30 50 mV/V and 6.3-9.1 mV/dec smaller than those of in situ doping devices at 25 nm Lg and a 9-11 nm thickness of SOl （Tsi）, respectively. The shift of Vtsat with Tsi for in situ doping devices with 15 nm Lg is -31.8 mV/nm, whereas that for in situ doping devices is only -6.8 mV/nm. These outcomes indicate that the devices with implanted doping can produce a more advanced and stable electrical performance.

Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor(CNT FET)has been considered as a promising candidate for future high-performance and low-power integrated circuits(ICs)applications owing to its ballistic transport and excellent immunity to short channel effects(SCEs).Still,it easily suffers from the ambipolar property,and severe leakage current at off-state originated from gate-induced drain leakage(GIDL)in CNT FETs with small bandgap.Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs,there is still a lack of the structure with excellent scalability,which will hamper the development of CNT FETs toward a competitive technology node.Here,we explore how the device geometry design affects the leakage current in CNT FETs,and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional(2D)TCAD simulations.Among all the proposed structures,the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process.According to the simulation results,the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/μm and an on-current as high as about 2.1 mA/μm at a supply voltage of-1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

An anisotropic thermal-stress model for through-silicon via

A two-dimensional thermal-stress model of through-silicon via（TSV） is proposed considering the anisotropic elastic property of the silicon substrate. By using the complex variable approach, the distribution of thermalstress in the substrate can be characterized more accurately. TCAD 3-D simulations are used to verify the model accuracy and well agree with analytical results（＆lt; ±5%）. The proposed thermal-stress model can be integrated into stress-driven design flow for 3-D IC, leading to the more accurate timing analysis considering the thermal-stress effect.

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism（NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS） and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are：（1） with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.（2） Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style（i.e.spacing between transistors and n-well contact area）.（3） Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.