In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a...In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.展开更多
Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, fo...Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.展开更多
The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient...The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.展开更多
基金supported by the National Key Research and Development Program of China(2021YFB2011700).
文摘In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.
基金Sponsored by the National Natural Science Foundation of China(No.61271149)
文摘Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via （TSV） with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance （RLGC） model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.
文摘The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.
