In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a...In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.展开更多
硅通孔(Through Si Vias,TSV)硅转接基板技术作为先进封装的一种工艺方式,是实现千级IO芯片高密度组装的有效途径,近年来在系统集成领域得到快速应用。TSV硅转接基板的细线条和与芯片相近的热导率可以解决陶瓷基板和芯片之间线宽和热导...硅通孔(Through Si Vias,TSV)硅转接基板技术作为先进封装的一种工艺方式,是实现千级IO芯片高密度组装的有效途径,近年来在系统集成领域得到快速应用。TSV硅转接基板的细线条和与芯片相近的热导率可以解决陶瓷基板和芯片之间线宽和热导率不匹配的问题。随着硅基板技术的推广,其可靠性评价是应用前急需解决的问题。目前并没有关于TSV硅转接基板的可靠性评价要求的国内相关标准。从TSV硅转接基板的结构出发,借鉴国军标相关标准,形成了针对硅转接基板的可靠性评价方法,并进行了工程验证。验证结果表明通过有针对性的评价方法,可以反映出TSV硅转接基板的质量特性,实现可靠性评价。展开更多
基金supported by the National Key Research and Development Program of China(2021YFB2011700).
文摘In three-dimensional(3D)stacking,the thermal stress of through-silicon via(TSV)has a significant influence on chip performance and reliability,and this problem is exacerbated in high-density TSV arrays.In this study,a novel hollow tungsten TSV(W-TSV)is presented and developed.The hollow structure provides space for the release of thermal stress.Simulation results showed that the hollow W-TSV structure can release 60.3%of thermal stress within the top 2 lm from the surface,and thermal stress can be decreased to less than 20 MPa in the radial area of 3 lm.The ultra-high-density(1600 TSV∙mm2)TSV array with a size of 640×512,a pitch of 25 lm,and an aspect ratio of 20.3 was fabricated,and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances.The average resistance of the TSV was 1.21 X.The leakage current was 643 pA and the breakdown voltage was greater than 100 V.The resistance change is less than 2%after 100 temperature cycles from40 to 125℃.Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa,which means that there was no keep-out zone(KOZ)caused by the TSV array.These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.
文摘硅通孔(Through Si Vias,TSV)硅转接基板技术作为先进封装的一种工艺方式,是实现千级IO芯片高密度组装的有效途径,近年来在系统集成领域得到快速应用。TSV硅转接基板的细线条和与芯片相近的热导率可以解决陶瓷基板和芯片之间线宽和热导率不匹配的问题。随着硅基板技术的推广,其可靠性评价是应用前急需解决的问题。目前并没有关于TSV硅转接基板的可靠性评价要求的国内相关标准。从TSV硅转接基板的结构出发,借鉴国军标相关标准,形成了针对硅转接基板的可靠性评价方法,并进行了工程验证。验证结果表明通过有针对性的评价方法,可以反映出TSV硅转接基板的质量特性,实现可靠性评价。
