Robust Watermarking with Kernels-Alternated Error Diffusion and Weighted Lookup Table in Halftone Images

A halftone watermarking method of high quality, robustness, and capacity flexibility is presented in this paper. An objective halftone image quality evaluation method based on the human visual system obtained by a least-mean-square algorithm is also introduced. In the encoder, the kernels-alternated error diffusion （KAEDF） is applied. It is able to maintain the computational complexity at the same level as ordinary error diffusion. Compared with Hel-Or using ordered dithering, the proposed KAEDF yields a better image quality through using error diffusion. We also propose a weighted lookup table （WLUT） in the decoder instead of lookup table （LUT）, as proposed by Pei and Guo, so as to achieve a higher decoded rate. As the experimental results demonstrate, this technique is able to guard against degradation due to tampering, cropping, rotation, and print-and-scan processes in error-diffused halftone images.

A complete lookup table for marching cubes

The well-known marching cubes method is used to generate isosurfaces from volume data or data on a 3D rectilinear grid. To do so, it refers to a lookup table to decide on the possible configurations of the isosurface within a given cube, assuming we know whether each vertex lies inside or outside the surface. However, the vertex values alone do not uniquely determine how the isosurface may pass through the cube, and in particular how it cuts each face of the cube. Earlier lookup tables are deficient in various respects. The possible combinations of the different configurations of such ambiguous faces are used in this paper to find a complete and cor- rect lookup table. Isosurfaces generated using the new lookup table here are guaranteed to be watertight.

Enhanced Portable LUT Multiplier with Gated Power Optimization for Biomedical Therapeutic Devices

Digital design of a digital signal processor involves accurate and high-speed mathematical computation units.DSP units are one of the most power consuming and memory occupying devices.Multipliers are the common building blocks in most of the DSP units which demands low power and area constraints in the field of portable biomedical devices.This research works attempts multiple power reduction technique to limit the power dissipation of the proposed LUT multiplier unit.A lookup table-based multiplier has the advantage of almost constant area requirement’s irrespective to the increase in bit size of multiplier.Clock gating is usually used to reduce the unnecessary switching activities in idle circlet components.A clock tree structure is employed to enhance the SRAM based lookup table memory architecture.The LUT memory access operation is sequential in nature and instead of address decoder a ring counter is used to scan the memory contents and gated driver tree structure is implemented to control the clock and data switching activities.The proposed algorithm yields 20%of power reduction than existing.

Accelerating Packet Classification with Counting Bloom Filters for Virtual Open Flow Switching

The growing trend of network virtualization results in a widespread adoption of virtual switches in virtualized environments. However, virtual switching is confronted with great performance challenges regarding packet classification especially in Open Flow-based software defined networks. This paper first takes an insight into packet classification in virtual Open Flow switching, and points out that its performance bottleneck is dominated by flow table traversals of multiple failed mask probing for each arrived packet. Then we are motivated to propose an efficient packet classification algorithm based on counting bloom filters. In particular, counting bloom filters are applied to predict the failures of flow table lookups with great possibilities, and bypass flow table traversals for failed mask probing. Finally, our proposed packet classification algorithm is evaluated with real network traffic traces by experiments. The experimental results indicate that our proposed algorithm outperforms the classical one in Open v Switch in terms of average search length, and contributes to promote virtual Open Flow switching performance.

Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

A region segmentation based algorithm for building a crystal position lookup table in a scintillation detector

In a scintillation detector, scintillation crystals are typically made into a 2-dimensional modular array. The location of incident gamma-ray needs be calibrated due to spatial response nonlinearity. Generally, position histograms--the characteristic flood response of scintillation detectors are used for position calibration. In this paper, a position calibration method based on a crystal position lookup table which maps the inaccurate location calculated by Anger logic to the exact hitting crystal position has been proposed. Firstly, the position histogram is preprocessed, such as noise reduction and image enhancement. Then the processed position histogram is segmented into disconnected regions, and crystal marking points are labeled by finding the centroids of regions. Finally, crystal boundaries are determined and the crystal position lookup table is generated. The scheme is evaluated by the whole-body positron emission tomography （PET） scanner and breast dedicated single photon emission computed tomography scanner developed by the Institute of High Energy Physics, Chinese Academy of Sciences. The results demonstrate that the algorithm is accurate, efficient, robust and applicable to any configurations of scintillation detector.

Design of Hybrid True Random Number Generator for Cryptographic Applications

In real-time applications,unpredictable random numbers play a major role in providing cryptographic and encryption processes.Most of the existing random number generators are embedded with the complex nature of an amplifier,ring oscillators,or comparators.Hence,this research focused more on implementing a Hybrid Nature of a New Random Number Generator.The key objective of the proposed methodology relies on the utilization of True random number generators.The randomness is unpredictable.The additions of programmable delay lines will reduce the processing time and maintain the quality of randomizing.The performance comparisons are carried out with power,delay,and lookup table.The proposed architecture was executed and verified using Xilinx.The Hybrid TRNG is evaluated under simulation and the obtained results outperform the results of the conventional random generators based on Slices,area and Lookup Tables.The experimental observations show that the proposed Hybrid True Random Number Generator(HTRNG)offers high operating speed and low power consumption.

A Novel Hybrid Encryption Method Based on Honey Encryption and Advanced DNA Encoding Scheme in Key Generation

Nowadays, increased information capacity and transmission processes make information security a difficult problem. As a result, most researchers employ encryption and decryption algorithms to enhance information security domains. As it progresses, new encryption methods are being used for information security. In this paper, a hybrid encryption algorithm that combines the honey encryption algorithm and an advanced DNA encoding scheme in key generation is presented. Deoxyribonucleic Acid (DNA) achieves maximal protection and powerful security with high capacity and low modification rate, it is currently being investigated as a potential carrier for information security. Honey Encryption (HE) is an important encryption method for security systems and can strongly prevent brute force attacks. However, the traditional honeyword encryption has a message space limitation problem in the message distribution process. Therefore, we use an improved honey encryption algorithm in our proposed system. By combining the benefits of the DNA-based encoding algorithm with the improved Honey encryption algorithm, a new hybrid method is created in the proposed system. In this paper, five different lookup tables are created in the DNA encoding scheme in key generation. The improved Honey encryption algorithm based on the DNA encoding scheme in key generation is discussed in detail. The passwords are generated as the keys by using the DNA methods based on five different lookup tables, and the disease names are the input messages that are encoded by using the honey encryption process. This hybrid method can reduce the storage overhead problem in the DNA method by applying the five different lookup tables and can reduce time complexity in the existing honey encryption process.

WBZUC:novel white-box ZUC-128 stream cipher

White-box cryptography is critical in a communication system to protect the secret key from being disclosed in a cryptographic algorithm code implementation.The stream cipher is a main dataflow encryption approach in mobile communication.However,research work on white-box cryptographic implementation for stream cipher is rare.A new white-box Zu Chongzhi-128(ZUC-128)cryptographic implementation algorithm named WBZUC was proposed.WBZUC adopts lookup table and random coding in the non-linear function to make the intermediate value chaotic without changing the final encryption result.Thus,the WBZUC algorithm’s security gets improved compared with the original ZUC-128 algorithm.As for the efficiency,a test experiment on WBZUC shows that the average speed of key generation,encryption,and decryption can reach at 33.74 kbit/s,23.31 kbit/s,24.06 kbit/s respectively.Despite its running speed is relatively a bit lower than original ZUC-128 algorithm,WBZUC can provide better security and comprehensive performance in mobile communication system environment.

Fast processing method to generate gigabyte computer generated holography for three-dimensional dynamic holographic display

Two different methods from graphic processing unit （GPU） and central processing unit （CPU） are proposed to suitably optimize look-up table algorithms of computer generated holography （CGH）. The numerical simula- tions and experimental results show that we can reconstruct a good quality object. The computation of CGH for a three-dimensional （3D） dynamic holographic display can also be sped up by programming with our proposed method. It can optimize both file loading and the inline calculation process. The phase-only CGH with gigabyte data for reconstructing 10 MB object samplings is generated. In addition, the proposed method effectively re- duced time costs of loading and writing offline tables on a CPU. It is believed the proposed method can provide high speed and huge data CGH for 3D dynamic holographic displays in the near future.

OFDM visible light communication transmitter based on LED array

In this letter, we present a scheme generating OFDM signals in optical domain instead of electrical domain by transmitting subcarrier signals with multiple LEDs. According to the simulation, this scheme can effectively eliminate signal degradation caused by the high peak-to-average power ratio of OFDM signals in traditional transmitter. Computational complexity in digital part of the transmitter can be reduced by using look-uo table. Receiver will stay unchanged.

Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.

Latent discriminative representation learning for speaker recognition

Extracting discriminative speaker-specific representations from speech signals and transforming them into fixed length vectors are key steps in speaker identification and verification systems.In this study,we propose a latent discriminative representation learning method for speaker recognition.We mean that the learned representations in this study are not only discriminative but also relevant.Specifically,we introduce an additional speaker embedded lookup table to explore the relevance between different utterances from the same speaker.Moreover,a reconstruction constraint intended to learn a linear mapping matrix is introduced to make representation discriminative.Experimental results demonstrate that the proposed method outperforms state-of-the-art methods based on the Apollo dataset used in the Fearless Steps Challenge in INTERSPEECH2019 and the TIMIT dataset.