A new design method interleavers, 2-dimension interleavers, are proposed for interleave division multiple access （IDMA） systems. With a same interleaving rule named I＇, the row indices and column indices of a tradi...A new design method interleavers, 2-dimension interleavers, are proposed for interleave division multiple access （IDMA） systems. With a same interleaving rule named I＇, the row indices and column indices of a traditional block interleaving matrix are scrambled to obtain an interleaver, which is marked as the master interleaver. F is produced by a loworder PN sequence generator. Two ways are provided for generating different interleavers. One is that all interleavers are generated by the circular shifting master interleaver. The other is that different inter leavers are generated by different Ts. Besides, we prove that the minimum distance between two adjacent bits resulted from 2-dimension interleaves is much larger than that of other schemes, such as random interleavers, power interleavers, and shiffting interleaves. The simulation results show that 2-dimension interleavers can achieve much better performance with much less resource consumption than random interleavers in IDMA systems.展开更多
Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mes...Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.展开更多
基金supported by the National Key Lab. Research Foundation of China under Grant No.2007CB310604
文摘A new design method interleavers, 2-dimension interleavers, are proposed for interleave division multiple access （IDMA） systems. With a same interleaving rule named I＇, the row indices and column indices of a traditional block interleaving matrix are scrambled to obtain an interleaver, which is marked as the master interleaver. F is produced by a loworder PN sequence generator. Two ways are provided for generating different interleavers. One is that all interleavers are generated by the circular shifting master interleaver. The other is that different inter leavers are generated by different Ts. Besides, we prove that the minimum distance between two adjacent bits resulted from 2-dimension interleaves is much larger than that of other schemes, such as random interleavers, power interleavers, and shiffting interleaves. The simulation results show that 2-dimension interleavers can achieve much better performance with much less resource consumption than random interleavers in IDMA systems.
基金supported by the National Natural Science Foundation of China under Grant No.60425413
文摘Networks-on-chip （NoC）, a new system on chip （SoC） paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh （2DDgl-Mesh） for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 （a network simulator） and CINS1M （a component based interconnection simulator） under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models.
