A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

Antichains and their application for enumerating ternary logic functions

MUKAIDONO proposed and systematically investigated the theory of regular ternary logic functions that meets the need of uncertain inferences. The enumeration of ternary logic functions is very complicated and several results have been obtained only in the case where the number of variables is less than 7. In this letter we offer a new possible way to solve the prob-

Ternary logic circuit design based on single electron transistors

Based on the I-V characteristics and the function of adjustable threshold voltage of a single electron transistor （SET）, we design the basic ternary logic circuits, which have been simulated by SPICE and their power and transient characteristics have been extensively analyzed. The simulation results indicate that the proposed circuits exhibit a simpler structure, smaller signal delay and lower power.

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

DESIGN OF TERNARY ADIABATIC MULTIPLIER ON SWITCH-LEVEL

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be ob-tained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ter-nary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are charac-terized with distinctive low power consumption.

Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.

A novel ternary JK flip-flop using the resonant tunneling diode literal circuit

A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes(RTDs).It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation.A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation,and the JK flip-flop also has two optional types of output structure.The design of the ternary RTD JK flip-flop is verified by simulation.The RTD literal circuit is the key design component for achieving various types of multi-valued logic(MVL) flip-flops.It can be converted into ternary D and JK flip-flops,and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships.All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations.This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.