Fabrication of Bottom-Gate and Top-Gate Transparent ZnO Thin Film Transistors

Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.

Influence of High Temperature Treatment on the Performance of Nickel-Induced Laterally Crystallized Thin Film Transistors

Well known for their good performance,thin film transistors (TFTs) with active layers which were nickel induced laterally crystallized,are fabricated by conventional process of dual gate CMOS.The influence of pre high temperature treatment of device fabrication on the performance of TFTs is also investigated.The experiment shows that the high temperature treatment affects the performance of the devices strongly.The best performance is obtained by adopting pre treatment of 1000℃.The mobility of 314cm 2/(V·s) is obtained at NMOS TFTs with pre treatment of 1000℃,which is 10% and 22% higher than that treated at 1100℃ and without pre high temperature treatment,respectively.A maximum on/off current ratio of 3×10 8 is also obtained at 1000℃.Further investigation of uniformity verifies that the result is reliable.

双层结构对ZnO TFT稳定性的影响

室温下采用射频磁控溅射方法在SiO_(2)/Si衬底上沉积了单层ZnO薄膜和高氧/低氧双层ZnO薄膜,采用电子束蒸发设备蒸镀Al电极,制备单沟道ZnO TFTs和双层沟道ZnO TFTs。比较两种结构ZnO TFTs的各种性能参数,分析双层结构对TFTs产生的影响。实验结果表明,底部高含氧量ZnO层和顶部低含氧量ZnO层构成了DAL同质结且高氧/低氧薄膜存在载流子浓度产差,利用载流子从高浓度向低浓度扩散的性质,可以填补栅介电层和沟道层之间的界面态缺陷,使器件界面类受主陷阱减少,有效降低TFTs的滞回现象。与单有源层TFTs相比,双沟道层TFTs还具有电学调制作用,其电学性能和稳定性均有明显的提高,得到最佳TFTs的开/关电流比达到3.44×10^(9),亚阈值摆幅为0.68 V/dec,阈值电压偏移为1.2 V。

Positive gate-bias temperature instability of ZnO thin-film transistor

The positive gate-bias temperature instability of a radio frequency （RF） sputtered ZnO thin-film transistor （ZnO TFT） is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.

Atomic layer deposition for nanoscale oxide semiconductor thin film transistors:review and outlook

Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.

Effects of active layer thickness on performance and stability of dual-active-layer amorphous InGaZnO thin-film transistors

Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.

Characteristics and Time-Dependent Instability of Ga-Doped ZnO Thin Film Transistor Fabricated by Radio Frequency Magnetron Sputtering

We report on the fabrication and electrical characteristics of Ga-doped ZnO thin film transistors(TFTs).Low Ga-doped(0.7wt%)ZnO thin films were deposited on SiO_(2)/p−Si substrates by rf magnetron sputtering.The GZO TFTs show a mobility of 1.76 cm2/V⋅s,an on/off ratio of 1.0×10^(6),and a threshold voltage of 35 V.The time−dependent instability of the TFT is studied.The VTH shifts negatively.In addition,the device shows a decrease of the on/off ratio,mainly due to the increase of the off-current.The mechanisms of instability are discussed.

High-photosensitivity polymer thin-film transistors based on poly(3-hexylthiophene)

Polymer thin-film transistors （PTFTs） based on poly（3-hexylthiophene） are fabricated by the spin-coating process, and their photo-sensing characteristics are investigated under steady-state visible-light illumination. The photosensitivity of the device is strongly modulated by gate voltage under various illuminations. When the device is in the subthreshold operating mode, a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10^3 at an illumination intensity of 1200 lx, and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx. However, when the device is in the on-state operating mode, the photosensitivity is very low： only 1.88 at an illumination intensity of 1200 lx for a gate voltage of -20 V and a drain voltage of -20 V. The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light. The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.

Simulation of grain boundary effect on characteristics of ZnO thin film transistor by considering the location and orientation of grain boundary

The grain boundaries （GBs） have a strong effect on the electric properties of ZnO thin film transistors （TFTs）. A novel grain boundary model was developed to analyse the effect. The model was characterized with different angles between the orientation of the grain boundary and the channel direction. The potential barriers formed by the grain boundaries increase with the increase of the grain boundary angle, so the degradation of the transistor characteristics increases. When a grain boundary is close to the drain edge, the potential barrier height reduces, so the electric properties were improved.

Self-assembled monolayers enhance the performance of oxide thin-film transistors

Thin-film transistors(TFTs)based on oxide semiconductors have gained a lot of attention in applications such as displays and sensors particularly in recent years due to the advantages of oxide semiconductors like high mobility,good uniformity over large area and low deposition temperature[1−4].However,the defects/traps at dielectric/channel interface and top surface of oxide TFTs might dramatically degrade device performance including current on/off ratio,mobility and most importantly stability[5,6],making it quite urgent to systematically make effective interface engineering to improve TFT performance.

Preparation and operation characteristics of organic semiconductor transistor using thin film Al gate and copper phthalocyanine

The organic static induction transistors (OSITs) are fabricated by the method of evaporating and plating in a vacuum with copper phthalocyanine (CuPc) dye, and has a five layered structure of Au/CuPc/Al/CuPc/Au. The experiment reveals that OSITs have obtained a low driving voltage, high current density and high switch speed such as I_ DS = 1.2×10 -6 A/mm2, and the degree of 1 000 Hz. The OSITs have excellent operation characteristics of typical static induction transistors.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

Carrier Transport Across Grain Boundaries in Polycrystalline Silicon Thin Film Transistors

We established a model for investigating polycrystalline silicon（poly-Si） thin film transistors（TFTs）.The effect of grain boundaries（GBs） on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region,and the dominant transport mechanism of carrier across grain boundaries was subsequently determined.It is shown that the thermionic emission（TE） is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary.To a poly-Si TFT model with a 1 nm-width grain boundary,in the linear region,thermionic emission is similar to that of tunneling（TU）,however,with increasing grain boundary width and number,tunneling becomes dominant.

High-Performance Photo-Modulated Thin-Film Transistor Based on Quantum dots/Reduced Graphene Oxide Fragment-Decorated ZnO Nanowires

In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of Cd Se quantum dots and reduced graphene oxide(RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 AW^(-1) and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.

有源层厚度对Li-ZTO TFT电学性能的影响

本研究旨在制备Li-ZTO单有源层薄膜晶体管,并研究有源层厚度对其性能的影响。该研究采用磁控溅射方法,使用Li-ZTO靶材制备出了有源层厚度分别为70 nm,90 nm,110 nm的器件。采用了X射线光电子能谱(XPS)、原子粒显微镜(AFM)、X射线衍射仪(XRD)等设备对制备出的Li-ZTO薄膜进行测试分析。通过对不同有源层厚度的薄膜物质组成、表面形貌、晶粒生长情况的测试分析,进一步研究了有源层厚度对Li-ZTO薄膜性能的影响。除此之外,我们还利用半导体参数仪对Li-ZTO的电学性能进行了测试。结果表明,过厚的有源层将影响电荷传输,增加散射中心,影响器件性能。因此,有源层厚度为70 nm的Li-ZTO具有最好的性能,包括12.33 cm^(2)/vs的饱和迁移率、0.66 V的阈值电压、2.12 V/dec的亚阈值摆幅以及>10~8的开关比。

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

Si-doped zinc oxide（SZO） thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10^-12 A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10^6 and superior stability under gate-bias and drain-bias stress.

Effects of annealing process on characteristics of fully transparent zinc tin oxide thin-film transistor

Annealing effect on the performance of fully transparent thin-film transistor （TTFT）, in which zinc tin oxide （ZnSnO） is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/（V.s） and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.

High-throughput fabrication and semi-automated characterization of oxide thin film transistors

High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.

Temperature-dependent bias-stress-induced electrical instability of amorphous indium-gallium-zinc-oxide thin-film transistors

The time and temperature dependence of threshold voltage shift under positive-bias stress（PBS） and the following recovery process are investigated in amorphous indium-gallium-zinc-oxide（a-IGZO） thin-film transistors. It is found that the time dependence of threshold voltage shift can be well described by a stretched exponential equation in which the time constant τ is found to be temperature dependent. Based on Arrhenius plots, an average effective energy barrier Eτ stress= 0.72 eV for the PBS process and an average effective energy barrier Eτ recovery= 0.58 eV for the recovery process are extracted respectively. A charge trapping/detrapping model is used to explain the threshold voltage shift in both the PBS and the recovery process. The influence of gate bias stress on transistor performance is one of the most critical issues for practical device development.

Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

The instability of p-channel low-temperature polycrystalline silicon thin film transistors(poly-Si TFTs)is investigated under negative gate bias stress(NBS)in this work.Firstly,a series of negative bias stress experiments is performed,the significant degradation behaviors in current-voltage characteristics are observed.As the stress voltage decreases from-25 V to-37 V,the threshold voltage and the sub-threshold swing each show a continuous shift,which is induced by gate oxide trapped charges or interface state.Furthermore,low frequency noise(LFN)values in poly-Si TFTs are measured before and after negative bias stress.The flat-band voltage spectral density is extracted,and the trap concentration located near the Si/SiO2 interface is also calculated.Finally,the degradation mechanism is discussed based on the current-voltage and LFN results in poly-Si TFTs under NBS,finding out that Si-OH bonds may be broken and form Si*and negative charge OH-under negative bias stress,which is demonstrated by the proposed negative charge generation model.