Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compos...Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.展开更多
Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficu...Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.展开更多
Indium-tin-zinc oxide(ITZO)thin-film transistor(TFT)technology holds promise for achieving high mobility and offers significant opportunities for commercialization.This paper provides a review of progress made in impr...Indium-tin-zinc oxide(ITZO)thin-film transistor(TFT)technology holds promise for achieving high mobility and offers significant opportunities for commercialization.This paper provides a review of progress made in improving the mobility of ITZO TFTs.This paper begins by describing the development and current status of metal-oxide TFTs,and then goes on to explain the advantages of selecting ITZO as the TFT channel layer.The evaluation criteria for TFTs are subsequently introduced,and the reasons and significance of enhancing mobility are clarified.This paper then explores the development of high-mobility ITZO TFTs from five perspectives:active layer optimization,gate dielectric optimization,electrode optimization,interface optimization,and device structure optimization.Finally,a summary and outlook of the research field are presented.展开更多
As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this w...As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this work,the triggering voltage of HCS-induced self-heating(SH)degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO)TFTs,and used to quantitatively evaluate the thermal generation process of channel donor defects.The fluorinated a-IGZO(a-IGZO:F)was adopted to effectively retard the triggering of the self-heating(SH)effect,and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F.The proposed scheme noticeably enhances the high-current applications of oxide TFTs.展开更多
Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Co...Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.展开更多
The positive gate-bias temperature instability of a radio frequency (RF) sputtered ZnO thin-film transistor (ZnO TFT) is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state cu...The positive gate-bias temperature instability of a radio frequency (RF) sputtered ZnO thin-film transistor (ZnO TFT) is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.展开更多
Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer con...Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.展开更多
We report on the fabrication and electrical characteristics of Ga-doped ZnO thin film transistors(TFTs).Low Ga-doped(0.7wt%)ZnO thin films were deposited on SiO_(2)/p−Si substrates by rf magnetron sputtering.The GZO T...We report on the fabrication and electrical characteristics of Ga-doped ZnO thin film transistors(TFTs).Low Ga-doped(0.7wt%)ZnO thin films were deposited on SiO_(2)/p−Si substrates by rf magnetron sputtering.The GZO TFTs show a mobility of 1.76 cm2/V⋅s,an on/off ratio of 1.0×10^(6),and a threshold voltage of 35 V.The time−dependent instability of the TFT is studied.The VTH shifts negatively.In addition,the device shows a decrease of the on/off ratio,mainly due to the increase of the off-current.The mechanisms of instability are discussed.展开更多
Polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process, and their photo-sensing characteristics are investigated under steady-state visible-light illuminat...Polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process, and their photo-sensing characteristics are investigated under steady-state visible-light illumination. The photosensitivity of the device is strongly modulated by gate voltage under various illuminations. When the device is in the subthreshold operating mode, a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10^3 at an illumination intensity of 1200 lx, and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx. However, when the device is in the on-state operating mode, the photosensitivity is very low: only 1.88 at an illumination intensity of 1200 lx for a gate voltage of -20 V and a drain voltage of -20 V. The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light. The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.展开更多
The grain boundaries (GBs) have a strong effect on the electric properties of ZnO thin film transistors (TFTs). A novel grain boundary model was developed to analyse the effect. The model was characterized with di...The grain boundaries (GBs) have a strong effect on the electric properties of ZnO thin film transistors (TFTs). A novel grain boundary model was developed to analyse the effect. The model was characterized with different angles between the orientation of the grain boundary and the channel direction. The potential barriers formed by the grain boundaries increase with the increase of the grain boundary angle, so the degradation of the transistor characteristics increases. When a grain boundary is close to the drain edge, the potential barrier height reduces, so the electric properties were improved.展开更多
Thin-film transistors(TFTs)based on oxide semiconductors have gained a lot of attention in applications such as displays and sensors particularly in recent years due to the advantages of oxide semiconductors like high...Thin-film transistors(TFTs)based on oxide semiconductors have gained a lot of attention in applications such as displays and sensors particularly in recent years due to the advantages of oxide semiconductors like high mobility,good uniformity over large area and low deposition temperature[1−4].However,the defects/traps at dielectric/channel interface and top surface of oxide TFTs might dramatically degrade device performance including current on/off ratio,mobility and most importantly stability[5,6],making it quite urgent to systematically make effective interface engineering to improve TFT performance.展开更多
An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors(a-IGZO TFTs)with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating mo...An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors(a-IGZO TFTs)with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance(C_(TI)/C_(BI)).Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.展开更多
We established a model for investigating polycrystalline silicon(poly-Si) thin film transistors(TFTs).The effect of grain boundaries(GBs) on the transfer characteristics of TFT was analyzed by considering the nu...We established a model for investigating polycrystalline silicon(poly-Si) thin film transistors(TFTs).The effect of grain boundaries(GBs) on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region,and the dominant transport mechanism of carrier across grain boundaries was subsequently determined.It is shown that the thermionic emission(TE) is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary.To a poly-Si TFT model with a 1 nm-width grain boundary,in the linear region,thermionic emission is similar to that of tunneling(TU),however,with increasing grain boundary width and number,tunneling becomes dominant.展开更多
In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of Cd Se...In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of Cd Se quantum dots and reduced graphene oxide(RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 AW^(-1) and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.展开更多
High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other para...High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.展开更多
Annealing effect on the performance of fully transparent thin-film transistor (TTFT), in which zinc tin oxide (ZnSnO) is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO acti...Annealing effect on the performance of fully transparent thin-film transistor (TTFT), in which zinc tin oxide (ZnSnO) is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/(V.s) and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.展开更多
基金supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NRF-2020M3H4A3081867)the industry technology R&D program (20006400) funded by the Ministry of Trade,Industry and Energy (MOTIE, Korea)+2 种基金the project number 20010402 funded by the Ministry of Trade,Industry and Energy (MOTIE, Korea)the Industry Technology R&D program (#20010371) funded by the Ministry of Trade,Industry and Energy (MOTIE, Republic of Korea)the Technology Innovation Program (20017382) funded By the Ministryof Trade,Industry and Energy (MOTIE, Korea)
文摘Since the first report of amorphous In–Ga–Zn–O based thin film transistors,interest in oxide semiconductors has grown.They offer high mobility,low off-current,low process temperature,and wide flexibility for compositions and processes.Unfortunately,depositing oxide semiconductors using conventional processes like physical vapor deposition leads to problematic issues,especially for high-resolution displays and highly integrated memory devices.Conventional approaches have limited process flexibility and poor conformality on structured surfaces.Atomic layer deposition(ALD)is an advanced technique which can provide conformal,thickness-controlled,and high-quality thin film deposition.Accordingly,studies on ALD based oxide semiconductors have dramatically increased recently.Even so,the relationships between the film properties of ALD-oxide semiconductors and the main variables associated with deposition are still poorly understood,as are many issues related to applications.In this review,to introduce ALD-oxide semiconductors,we provide:(a)a brief summary of the history and importance of ALD-based oxide semiconductors in industry,(b)a discussion of the benefits of ALD for oxide semiconductor deposition(in-situ composition control in vertical distribution/vertical structure engineering/chemical reaction and film properties/insulator and interface engineering),and(c)an explanation of the challenging issues of scaling oxide semiconductors and ALD for industrial applications.This review provides valuable perspectives for researchers who have interest in semiconductor materials and electronic device applications,and the reasons ALD is important to applications of oxide semiconductors.
基金supported by National Natural Science Foundation of China(No.U20A20209)Zhejiang Provincial Natural Science Foundation of China(LD19E020001)+1 种基金Zhejiang Provincial Key Research and Development Program(2021C01030)"Pioneer"and"Leading Goose"R&D Program of Zhejiang Province(2021C01SA301612)。
文摘Amorphous oxide semiconductors(AOS)have unique advantages in transparent and flexible thin film transistors(TFTs)applications,compared to low-temperature polycrystalline-Si(LTPS).However,intrinsic AOS TFTs are difficult to obtain field-effect mobility(μFE)higher than LTPS(100 cm^(2)/(V·s)).Here,we design ZnAlSnO(ZATO)homojunction structure TFTs to obtainμFE=113.8 cm^(2)/(V·s).The device demonstrates optimized comprehensive electrical properties with an off-current of about1.5×10^(-11)A,a threshold voltage of–1.71 V,and a subthreshold swing of 0.372 V/dec.There are two kinds of gradient coupled in the homojunction active layer,which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility.Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.
基金financially supported in part by Shenzhen Municipal Research Program(Grant NO.SGDX20211123145404006)in part by National Natural Science Foundation of China(Grant NO.62274111)+1 种基金in part by Guangdong Basic and Applied Basic Research Foundation(Grant NO.2021A1515011858)in part by Innovation and Technology Fund of Hong Kong(Grant NO.GHP/018/21SZ)。
文摘Indium-tin-zinc oxide(ITZO)thin-film transistor(TFT)technology holds promise for achieving high mobility and offers significant opportunities for commercialization.This paper provides a review of progress made in improving the mobility of ITZO TFTs.This paper begins by describing the development and current status of metal-oxide TFTs,and then goes on to explain the advantages of selecting ITZO as the TFT channel layer.The evaluation criteria for TFTs are subsequently introduced,and the reasons and significance of enhancing mobility are clarified.This paper then explores the development of high-mobility ITZO TFTs from five perspectives:active layer optimization,gate dielectric optimization,electrode optimization,interface optimization,and device structure optimization.Finally,a summary and outlook of the research field are presented.
基金supported by National Key Research and Development Program under Grant No.2022YFB3607100Shenzhen Research Programs under Grant Nos.JCYJ20200109140601691,JCYJ20190808154803565,SGDX20201103095607022,SGDX20211123145404006,and GXWD20201231165807007-20200807025846001。
文摘As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this work,the triggering voltage of HCS-induced self-heating(SH)degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO)TFTs,and used to quantitatively evaluate the thermal generation process of channel donor defects.The fluorinated a-IGZO(a-IGZO:F)was adopted to effectively retard the triggering of the self-heating(SH)effect,and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F.The proposed scheme noticeably enhances the high-current applications of oxide TFTs.
基金Project supported by the National Natural Science Foundation of China (Grant No.61874029)。
文摘Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.
基金supported by the National Natural Science Foundation of China(Grant Nos.61076113 and 61274085)the Research Grants Council of Hong Kong,China(Grant No.7133/07E)
文摘The positive gate-bias temperature instability of a radio frequency (RF) sputtered ZnO thin-film transistor (ZnO TFT) is investigated. Under positive gate-bias stress, the saturation drain current and OFF-state current decrease, and the threshold voltage shifts toward the positive direction. The stress amplitude and stress temperature are considered as important factors in threshold-voltage instability, and the time dependences of threshold voltage shift under various bias temperature stress conditions could be described by a stretched-exponential equation. Based on the analysis of hysteresis behaviors in current- voltage and capacitance-voltage characteristics before and after the gate-bias stress, it can be clarified that the threshold- voltage shift is predominantly attributed to the trapping of negative charge carriers in the defect states located at the gate- dielectric/channel interface.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11674405,61874139,and 11675280)
文摘Dual-active-layer(DAL)amorphous InGaZnO(IGZO)thin-film transistors(TFTs)are fabricated at low temperature without post-annealing.A bottom low-resistance(low-R)IGZO layer and a top high-resistance(high-R)IGZO layer constitute the DAL homojunction with smooth and high-quality interface by in situ modulation of oxygen composition.The performance of the DAL TFT is significantly improved when compared to that of a single-active-layer TFT.A detailed investigation was carried out regarding the effects of the thickness of both layers on the electrical properties and gate bias stress stabilities.It is found that the low-R layer improves the mobility,ON/OFF ratio,threshold voltage and hysteresis voltage by passivating the defects and providing a smooth interface.The high-R IGZO layer has a great impact on the hysteresis,which changes from clockwise to counterclockwise.The best TFT shows a mobility of 5.41 cm^2/V·s,a subthreshold swing of 95.0 mV/dec,an ON/OFF ratio of 6.70×10^7,a threshold voltage of 0.24 V,and a hysteresis voltage of 0.13 V.The value of threshold voltage shifts under positive gate bias stress decreases when increasing the thickness of both layers.
基金Supported by the National Natural Science Foundation of China under Grant No 50972007the Beijing Municipal Natural Science Foundation under Grant No 4092035+2 种基金the National Basic Research Program of China under Grant No 2011CB932703the National Science Fund for Distinguished Young Scholars under Grant No 60825407the Special Items Fund of the Beijing Municipal Commission of Education,and the Opened Fund of the State Key Laboratory on Integrated Optoelectronics.
文摘We report on the fabrication and electrical characteristics of Ga-doped ZnO thin film transistors(TFTs).Low Ga-doped(0.7wt%)ZnO thin films were deposited on SiO_(2)/p−Si substrates by rf magnetron sputtering.The GZO TFTs show a mobility of 1.76 cm2/V⋅s,an on/off ratio of 1.0×10^(6),and a threshold voltage of 35 V.The time−dependent instability of the TFT is studied.The VTH shifts negatively.In addition,the device shows a decrease of the on/off ratio,mainly due to the increase of the off-current.The mechanisms of instability are discussed.
基金Projected supported by the National Natural Science Foundation of China (Grant No. 61076113)the Natural Science Foundation of Guangdong Province,China (Grant No. 8451064101000257)the Research Grants Council (RGC) of Hong Kong Special Administrative Region (HKSAR),China (Grant No. HKU 7133/07E)
文摘Polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process, and their photo-sensing characteristics are investigated under steady-state visible-light illumination. The photosensitivity of the device is strongly modulated by gate voltage under various illuminations. When the device is in the subthreshold operating mode, a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10^3 at an illumination intensity of 1200 lx, and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx. However, when the device is in the on-state operating mode, the photosensitivity is very low: only 1.88 at an illumination intensity of 1200 lx for a gate voltage of -20 V and a drain voltage of -20 V. The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light. The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.
基金supported by the National Natural Science Foundation of China (Grant Nos 50677014,50602014 and 10874042)the National High Technology Joint Research Program of China (Grant No 2006AA04A104)the Science-Technology Foundation of Hunan Province of China (Grant Nos 2008RS4003 and 07jj107)
文摘The grain boundaries (GBs) have a strong effect on the electric properties of ZnO thin film transistors (TFTs). A novel grain boundary model was developed to analyse the effect. The model was characterized with different angles between the orientation of the grain boundary and the channel direction. The potential barriers formed by the grain boundaries increase with the increase of the grain boundary angle, so the degradation of the transistor characteristics increases. When a grain boundary is close to the drain edge, the potential barrier height reduces, so the electric properties were improved.
基金W.Cai and Z.Zang thank National Natural Science Foundation of China(11974063)Natural Science Foundation of Chongqing(cstc2020jcyj-jqX0028)+2 种基金China Postdoctoral Science Foundation(2020M683242)and Chongqing Special Postdoctoral Science Foundation(cstc2020jcyj-bshX0123)for financial support.L.Ding thanks National Key Research and Development Program of China(2017YFA0206600)National Natural Science Foundation of China(51773045,21772030,51922032,and 21961160720)for financial support.
文摘Thin-film transistors(TFTs)based on oxide semiconductors have gained a lot of attention in applications such as displays and sensors particularly in recent years due to the advantages of oxide semiconductors like high mobility,good uniformity over large area and low deposition temperature[1−4].However,the defects/traps at dielectric/channel interface and top surface of oxide TFTs might dramatically degrade device performance including current on/off ratio,mobility and most importantly stability[5,6],making it quite urgent to systematically make effective interface engineering to improve TFT performance.
基金Supported by the National Key Research and Development Program of China under Grant No 2017YFA0204600the National Natural Science Foundation of China under Grant No 61404002the Science and Technology Project of Hunan Province under Grant No 2015JC3041
文摘An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors(a-IGZO TFTs)with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance(C_(TI)/C_(BI)).Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.
基金Funded by the National Natural Science Foundation of China(Nos.51202063 and 51177003)Hubei Provincial Department of Education(No.Q20111009)
文摘We established a model for investigating polycrystalline silicon(poly-Si) thin film transistors(TFTs).The effect of grain boundaries(GBs) on the transfer characteristics of TFT was analyzed by considering the number and the width of grain boundaries in the channel region,and the dominant transport mechanism of carrier across grain boundaries was subsequently determined.It is shown that the thermionic emission(TE) is dominant in the subthreshold operating region of TFT regardless of the number and the width of grain boundary.To a poly-Si TFT model with a 1 nm-width grain boundary,in the linear region,thermionic emission is similar to that of tunneling(TU),however,with increasing grain boundary width and number,tunneling becomes dominant.
基金partially supported by the National Key Basic Research Program 973 (2013CB328804, 2013CB328803)the National High-Tech R&D Program 863 of China (2012AA03A302, 2013AA011004)+4 种基金the National Natural Science Foundation Project (51120125001, 61271053, 61306140, 61405033, 91333118, 61372030, 61307077 and 51202028)the Beijing Natural Science Foundation (4144076)the China Postdoctoral Science Foundation (2013M530613 and 2015T80080)the Natural Science Foundation Project of Jiangsu Province (BK20141390, BK20130629, and BK20130618)the Scientific Research Department of Graduate School in Southeast University
文摘In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of Cd Se quantum dots and reduced graphene oxide(RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 AW^(-1) and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.
基金the National Renewable Energy Laboratory, operated by Alliance for Sustainable Energy, LLC, for the U.S. Department of Energy (DOE) under Contract No. DE-AC36-08GO28308Funding provided by Laboratory Directed Research and Development (LDRD) program at NREL. Y. H+1 种基金support from Science and Technology Commission of Shanghai Municipality (Grant No. 16JC1400603)a grant from the National Natural Science Foundation of China (Grant No. 61471126)
文摘High throughput experimental methods are known to accelerate the rate of research,development,and deployment of electronic materials.For example,thin films with lateral gradients in composition,thickness,or other parameters have been used alongside spatially-resolved characterization to assess how various physical factors affect the material properties under varying measurement conditions.Similarly,multi-layer electronic devices that contain such graded thin films as one or more of their layers can also be characterized spatially in order to optimize the performance.In this work,we apply these high throughput experimental methods to thin film transistors(TFTs),demonstrating combinatorial channel layer growth,device fabrication,and semi-automated characterization using sputtered oxide TFTs as a case study.We show that both extrinsic and intrinsic types of device gradients can be generated in a TFT library,such as channel thickness and length,channel cation compositions,and oxygen atmosphere during deposition.We also present a semi-automated method to measure the 44 devices fabricated on a 50 mm×50 mm substrate that can help to identify properly functioning TFTs in the library and finish the measurement in a short time.Finally,we propose a fully automated characterization system for similar TFT libraries,which can be coupled with high throughput data analysis.These results demonstrate that high throughput methods can accelerate the investigation of TFTs and other electronic devices.
基金Project supported by the National Natural Science Foundation of China (Grant Nos.61290305 and 91021020)the Natural Science Foundation of Zhejiang Province,China (Grant No.Z6100117)
文摘Annealing effect on the performance of fully transparent thin-film transistor (TTFT), in which zinc tin oxide (ZnSnO) is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/(V.s) and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.