Heterojunction-engineered carrier transport in elevated-metal metal-oxide thin-film transistors

This study investigates the carrier transport of heterojunction channel in oxide semiconductor thin-film transistor(TFT)using the elevated-metal metal-oxide(EMMO)architecture and indium−zinc oxide(InZnO).The heterojunction band diagram of InZnO bilayer was modified by the cation composition to form the two-dimensional electron gas(2DEG)at the interface quantum well,as verified using a metal−insulator−semiconductor(MIS)device.Although the 2DEG indeed contributes to a higher mobility than the monolayer channel,the competition and cooperation between the gate field and the built-in field strongly affect such mobility-boosting effect,originating from the carrier inelastic collision at the heterojunction interface and the gate field-induced suppression of quantum well.Benefited from the proper energy-band engineering,a high mobility of 84.3 cm2·V^(−1)·s^(−1),a decent threshold voltage(V_(th))of−6.5 V,and a steep subthreshold swing(SS)of 0.29 V/dec were obtained in InZnO-based heterojunction TFT.

Indispensable gutter layers in thin-film composite membranes for carbon capture

Industrial thin-film composite(TFC)membranes achieve superior gas separation properties from high-performance selective layer materials,while the success of membrane technology relies on high-performance gutter layers to achieve production scalability and low-cost manufacturing.However,the current literature predominantly focuses on the design of polymer architectures to obtain high permeability and selectivity,while the art of fabricating gutter layers is usually safeguarded by industrial manufacturers and appears lackluster to academic researchers.This is the first report aiming to provide a comprehensive and critical review of state-of-the-art gutter layer materials and their design and modification to enable TFC membranes with superior separation performance.We first elucidate the importance of the gutter layer on membrane performance through modeling and experimental results.Then various gutter layer materials used to obtain high-performance composite membranes are critically reviewed,and the strategies to improve their compatibility with the selective layer are highlighted,such as oxygen plasma treatment,polydopamine deposition,and surface grafting.Finally,we present the opportunities of the gutter layer design for practical applications.

Implementation of sub-100 nm vertical channel-all-around(CAA) thin-film transistor using thermal atomic layer deposited IGZO channel

In-Ga-Zn-O(IGZO) channel based thin-film transistors(TFT), which exhibit high on-off current ratio and relatively high mobility, has been widely researched due to its back end of line(BEOL)-compatible potential for the next generation dynamic random access memory(DRAM) application. In this work, thermal atomic layer deposition(TALD) indium gallium zinc oxide(IGZO) technology was explored. It was found that the atomic composition and the physical properties of the IGZO films can be modulated by changing the sub-cycles number during atomic layer deposition(ALD) process. In addition, thin-film transistors(TFTs) with vertical channel-all-around(CAA) structure were realized to explore the influence of different IGZO films as channel layers on the performance of transistors. Our research demonstrates that TALD is crucial for high density integration technology, and the proposed vertical IGZO CAA-TFT provides a feasible path to break through the technical problems for the continuous scale of electronic equipment.

Numerical Study and Optimization of CZTS-Based Thin-Film Solar Cell Structure with Different Novel Buffer-Layer Materials Using SCAPS-1D Software

This study explored the performances of CZTS-based thin-film solar cell with three novel buffer layer materials ZnS, CdS, and CdZnS, as well as with variation in thickness of buffer and absorber-layer, doping concentrations of absorber-layer material and operating temperature. Our aims focused to identify the most optimal thin-film solar cell structure that offers high efficiency and lower toxicity which are desirable for sustainable and eco-friendly energy sources globally. SCAPS-1D, widely used software for modeling and simulating solar cells, has been used and solar cell fundamental performance parameters such as open-circuited voltage (), short-circuited current density (), fill-factor() and efficiency() have been optimized in this study. Based on our simulation results, it was found that CZTS solar cell with Cd0.4Zn0.6S as buffer-layer offers the most optimal combination of high efficiency and lower toxicity in comparison to other structure investigated in our study. Although the efficiency of Cd0.4Zn0.6S, ZnS and CdS are comparable, Cd0.4Zn0.6S is preferable to use as buffer-layer for its non-toxic property. In addition, evaluation of performance as a function of buffer-layer thickness for Cd0.4Zn0.6S, ZnS and CdS showed that optimum buffer-layer thickness for Cd0.4Zn0.6S was in the range from 50 to 150nm while ZnS offered only 50 – 75 nm. Furthermore, the temperature dependence performance parameters evaluation revealed that it is better to operate solar cell at temperature 290K for stable operation with optimum performances. This study would provide valuable insights into design and optimization of nanotechnology-based solar energy technology for minimizing global energy crisis and developing eco-friendly energy sources sustainable and simultaneously.

Numerical Analysis on the Effect of n-Si on Cu(In, Ga)Se2 Based Thin-Films for High-Performance Solar Cells by 1D-SCAPS

We report the performances of a chalcopyrite Cu(In, Ga)Se2 CIGS-based thin-film solar cell with a newly employed high conductive n-Si layer. The data analysis was performed with the help of the 1D-Solar Cell Capacitance Simulator (1D-SCAPS) software program. The new device structure is based on the CIGS layer as the absorber layer, n-Si as the high conductive layer, i-In2S3, and i-ZnO as the buffer and window layers, respectively. The optimum CIGS bandgap was determined first and used to simulate and analyze the cell performance throughout the experiment. This analysis revealed that the absorber layer’s optimum bandgap value has to be 1.4 eV to achieve maximum efficiency of 22.57%. Subsequently, output solar cell parameters were analyzed as a function of CIGS layer thickness, defect density, and the operating temperature with an optimized n-Si layer. The newly modeled device has a p-CIGS/n-Si/In2S3/Al-ZnO structure. The main objective was to improve the overall cell performance while optimizing the thickness of absorber layers, defect density, bandgap, and operating temperature with the newly employed optimized n-Si layer. The increase of absorber layer thickness from 0.2 - 2 µm showed an upward trend in the cell’s performance, while the increase of defect density and operating temperature showed a downward trend in solar cell performance. This study illustrates that the proposed cell structure shows higher cell performances and can be fabricated on the lab-scale and industrial levels.

Simulation of a Double-Gate Dynamic Threshold Voltage Fully Depleted Silicon-on-Insulator nMOSFET

A novel planar DGDT FDSOI nMOSFET is presented, and the operation mechanism is discussed. The device fabrication processes and characteristics are simulated with Tsuprem 4 and Medici. The back-gate n-well is formed by implantation of phosphorus at a dosage of 3 × 10^13 cm^-2 and an energy of 250keV and connected directly to a front-gate n^＋ polysilicon. This method is completely compatible with the conventional bulk silicon process. Simulation results show that a DGDT FDSOI nMOSFET not only retains the advantages of a conventional FDSOI nMOSFET over a partially depleted （PD） SOI nMOSFET--that is the avoidance of anomalous subthreshold slope and kink effects but also shows a better drivability than a conventional FDSOI nMOSFET.

Threshold Voltage Model of a Double-Gate MOSFET with Schottky Source and Drain

A quasi two-dimensional （2D） analytical model of a double-gate （DG） MOSFET with Schottky source/drain is developed based on the Poisson equation.The 2D potential distribution in the channel is calculated.An expression for threshold voltage for a short-channel DG MOSFET with Schottky S/D is also presented by defining the turn-on condition.The results of the model are verified by the numerical simulator DESSIS-ISE.

A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate （DG） MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.

Improved double-gate armchair silicene nanoribbon field-effect-transistor at large transport bandgap

The electrical characteristics of a double-gate armchair silicene nanoribbon field-effect-transistor （DG ASiNR FET） are thoroughly investigated by using a ballistic quantum transport model based on non-equilibrium Green＇s function （NEGF） approach self-consistently coupled with a three-dimensional （3D） Poisson equation. We evaluate the influence of variation in uniaxial tensile strain, ribbon temperature and oxide thickness on the on-off current ratio, subthreshold swing, transconductance and the delay time of a 12-nm-length ultranarrow ASiNR FET. A novel two-parameter strain mag- nitude and temperature-dependent model is presented for designing an optimized device possessing balanced amelioration of all the electrical parameters. We demonstrate that employing HfO2 as the gate insulator can be a favorable choice and simultaneous use of it with proper combination of temperature and strain magnitude can achieve better device performance. Furthermore, a general model power （GMP） is derived which explicitly provides the electron effective mass as a function of the bandgap of a hydrogen passivated ASiNR under strain.

All-Solid-State Thin-Film Lithium-Sulfur Batteries

Lithium-sulfur(Li-S)system coupled with thin-film solid electrolyte as a novel high-energy micro-battery has enormous potential for complementing embedded energy harvesters to enable the autonomy of the Internet of Things microdevice.However,the volatility in high vacuum and intrinsic sluggish kinetics of S hinder researchers from empirically integrating it into allsolid-state thin-film batteries,leading to inexperience in fabricating all-solid-state thin-film Li-S batteries(TFLSBs).Herein,for the first time,TFLSBs have been successfully constructed by stacking vertical graphene nanosheets-Li2S(VGsLi2S)composite thin-film cathode,lithium-phosphorous-oxynitride(LiPON)thin-film solid electrolyte,and Li metal anode.Fundamentally eliminating Lipolysulfide shuttle effect and maintaining a stable VGs-Li2S/LiPON interface upon prolonged cycles have been well identified by employing the solid-state Li-S system with an“unlimited Li”reservoir,which exhibits excellent longterm cycling stability with a capacity retention of 81%for 3,000 cycles,and an exceptional high temperature tolerance up to 60℃.More impressively,VGs-Li2S-based TFLSBs with evaporated-Li thin-film anode also demonstrate outstanding cycling performance over 500 cycles with a high Coulombic efficiency of 99.71%.Collectively,this study presents a new development strategy for secure and high-performance rechargeable all-solid-state thin-film batteries.

An improvement to computational efficiency of the drain current model for double-gate MOSFET

As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.

A novel 10-nm physical gate length double-gate junction field effect transistor

A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.

Stability of high-salinity-enhanced foam:Surface behavior and thin-film drainage

Cocamidopropyl hydroxyl sulfobetaine(CHSB)is one of the most promising foaming agents for high-salinity reservoirs because the salt in place facilitates its foam stability,even with salinity as high as 2×10^(5)mg/L.However,the synergistic effects between CHSB and salt have not been fully understood.This study utilized bulk foam tests and thin-film interferometry to comprehensively investigate the macroscopic and microscopic decay processes of CHSB foams with NaCl concentrations ranging from 2.3×10^(4)to 2.1×10^(5)mg/L.We focused on the dilatational viscoelasticity and dynamic thin-film thickness to elucidate the high-salinity-enhanced foam stability.The increase in dilatational viscoelasticity and supramolecular oscillating structural force(Π_(OS))with salinity dominated the superior stability of CHSB foam.With increasing salinity,more CHSB molecules accumulated on the surface with a lower diffusion rate,leading to high dilatational moduli and surface elasticity,thus decelerating coarsening and coalescence.Meanwhile,the number density of micelles in the thin film increased with salinity,resulting in increasedΠOS.Consequently,the energy barrier for stepwise thinning intensified,and the thin-film drainage slowed.This work conduces to understand the mechanisms behind the pronounced stability of betaine foam and can promote the widespread application of foam in harsh reservoirs.

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

This paper presents a compact two-dimensional analytical device model of surface potential,in addition to electric field of triple-material double-gate(TMDG)tunnel FET.The TMDG TFET device model is developed using a parabolic approximation method in the channel depletion space and a boundary state of affairs across the drain and source.The TMDG TFET device is used to analyze the electrical performance of the TMDG structure in terms of changes in potential voltage,lateral and vertical electric field.Because the TMDG TFET has a simple compact structure,the surface potential is computationally efficient and,therefore,may be utilized to analyze and characterize the gate-controlled devices.Furthermore,using Kane's model,the current across the drain can be modeled.The graph results achieved from this device model are close to the data collected from the technology computer aided design(TCAD)simulation.

Performance of Double-Pole Four-Throw Double-Gate RF CMOS Switch in 45-nm Technology

In this paper, we have investigated the design parameters of RF CMOS switch, which will be used for the wireless tele-communication systems. A double-pole four-throw double-gate radio-frequency complementary-metal-oxide-semicon- ductor (DP4T DG RF CMOS) switch for operating at the 1 GHz is implemented with 45-nm CMOS process technology. This proposed RF switch is capable to select the data streams from the two antennas for both the transmitting and receiving processes. For the development of this DP4T DG RF CMOS switch we have explored the basic concept of the proposed switch circuit elements required for the radio frequency systems such as drain current, threshold voltage, resonant frequency, return loss, transmission loss, VSWR, resistances, capacitances, and switching speed.

Capacitive Model and S-Parameters of Double-Pole Four-Throw Double-Gate RF CMOS Switch

In this paper, we have analyzed the Double-Pole Four-Throw Double-Gate Radio-Frequency Complementary Metal-Oxide-Semiconductor (DP4T DG RF CMOS) switch using S-parameters for 1 GHz to 60 GHz of frequency range. DP4T DG RF CMOS switch for operation at high frequency is also analyzed with its capacitive model. The re-sults for the development of this proposed switch include the basics of the circuit elements in terms of capacitance, re-sistance, impedance, admittance, series equivalent and parallel equivalent of this network at different frequencies which are present in this switch whatever they are ON or OFF.

Low-temperature metal–oxide thin-film transistor technologies for implementing flexible electronic circuits and systems

Here we review two 300℃metal–oxide(MO)thin-film transistor(TFT)technologies for the implementation of flexible electronic circuits and systems.Fluorination-enhanced TFTs for suppressing the variation and shift of turn-on voltage(VON),and dual-gate TFTs for acquiring sensor signals and modulating VON have been deployed to improve the robustness and performance of the systems in which they are deployed.Digital circuit building blocks based on fluorinated TFTs have been designed,fabricated,and characterized,which demonstrate the utility of the proposed low-temperature TFT technologies for implementing flexible electronic systems.The construction and characterization of an analog front-end system for the acquisition of bio-potential signals and an active-matrix sensor array for the acquisition of tactile images have been reported recently.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs),severe instabilities and even hard breakdown under high-current stress(HCS)become critical challenges.In this work,the triggering voltage of HCS-induced self-heating(SH)degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO)TFTs,and used to quantitatively evaluate the thermal generation process of channel donor defects.The fluorinated a-IGZO(a-IGZO:F)was adopted to effectively retard the triggering of the self-heating(SH)effect,and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F.The proposed scheme noticeably enhances the high-current applications of oxide TFTs.