基于流水线计算的3D NoC测试规划研究

为了提高三维片上网络(3D NoC)资源内核的测试效率,提出一种在功耗约束条件下多播流水线并行测试同构核与单播测试异构核相结合的方法对IP核进行测试。为了减少测试数据因资源冲突而进行等待的时间,设计一种改进XYZ路由算法,并采用改进人工蜂群(ABC)算法求解最佳测试规划方案。以国际标准电路测试集ITC'02作为实验对象,结果表明,测试时间最大优化率达到15.45%,与其他测试规划方法相比该文方法能有效地提高并行测试效率。

一种面向功耗免死锁三维全动态3D NoC路由算法

随着近年来三维片上网络(3D NoC)技术的提出及不断发展,功耗问题已成为3D NoC设计中面临的严峻挑战之一.本文为3DNoC提出一种面向功耗免死锁三维全动态路由算法TFRA(Three-dimensional Ful-l adaptive Rout-ing Algorithm).其以传统二维NoC奇偶拐弯模型为基础,将三维路由空间划分为8个象限,针对每个象限制定相应的路由策略,从而实现免死锁.采用SystemC系统级建模语言搭建的3D NoC仿真平台进行验证,结果显示TFRA算法在功耗性能指标方面较现有的三维路由算法有大幅提升.

基于时间Petri网和THBA的3D NoC测试规划

针对三维片上网络（3D NoC）中IP核并行测试任务复杂、测试效率较低的问题,结合3D NoC测试的特点建立了一种时间Petri网模型,将变迁激发序列作为并行测试任务规划方案。为了获得最短的测试时间,设计拆分编码,在测试路径分配基础上进行顺序调度优化,采用两级递阶蝙蝠算法对变迁激发序列集进行搜索,将测试资源合理有效的分配给各IP核。仿真结果表明,所提模型可以有效地描述3D NoC测试规划问题,算法能够以较大的收敛概率迅速收敛到最优解,缩短了测试时间,提高了测试效率。

基于粒子群算法的多约束3D NoC协同测试规划

为了提高三维片上网络(3D NoC)资源内核的测试效率,对多约束下的3D NoC进行测试规划。在硅通孔(TSV)数量、功耗以及带宽约束下,分别将TSV位置、IP核测试数据分配作为两个寻优变量,利用离散粒子群算法协同进化,以减少测试时间并提高TSV利用率。在算法中引入全局次优极值对粒子进行指导,提高全局搜索能力;并通过自适应参数调整策略增加种群多样性,从而改善粒子搜索的停滞现象。以国际标准测试集ITC'02中的电路作为仿真对象,仿真结果表明,算法能够有效地完成在多约束下对TSV位置的寻优并合理分配通信资源,缩短了测试时间,提高了TSV利用率。

基于猴群算法的3D NoC IP核测试优化方法

如何对三维片上网络(three Dimensional Network-on-Chip,3DNoC)资源内核的测试进行优化以缩短测试时间,提高资源利用率是当前3DNoC测试面临的主要问题之一.本文针对3DNoC IP核测试优化问题,开展TSV位置与IP核测试数据分配方案协同优化研究.在带宽、功耗和TSV数量约束下,将TSV位置方案和IP核测试数据分配方案作为寻优变量,采用猴群算法进行寻优.算法通过爬和望跳过程进行局部搜索并结合翻过程在不同领域进行搜索从而找到最优解,加入精英保留策略以确保算法收敛性,使算法搜索结果更为准确.以ITC’02电路为实验对象,实验结果表明,该算法能够有效地优化3DNoC资源分配,缩短测试时间,提高资源利用率.

硅通孔负载全局均衡的3D NoC延迟上界优化方法

针对三维片上网络(3D No C)中硅通孔(TSV)的特殊结构,提出了一种3D No C延迟上界优化方法,通过全局均衡硅通孔负载,降低全局业务流的延迟上界.建立3D No C的网格通信模型,搜索网络中所有业务流的可行路径,提出一种基于度的冲突矩阵,求出目标子流路径的TSV冲突系数,按照路径中TSV冲突系数的大小把目标流流量分配到部分最优路径上.实验结果表明,基于度的冲突矩阵可以有效减少存储空间,将存储复杂度从O(n2)降低到O(n),并且可以清晰直观地表现出业务流在网络中的冲突情况.采用硅通孔负载全局均衡的3D No C延迟上界优化方法,目标业务流的延迟上界得到了显著优化,最大的优化效果可将延迟上界降低58.9%.

3D NoC网络架构设计

在三维片上网络(3D NoC)设计中,层与层之间通信机制的优劣将影响整个3D NoC系统的性能。为此,在GEMS仿真平台基础上,提出一种低硬件资源消耗、高性能的总线架构,改进路由设计,构造基于总线的3D NoC的路由器。实验结果表明,该架构可提高常见算法的加速比,改善系统的整体性能。

Designing cost-effective network-on-chip by dual-channel access mechanism

A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.

Twist-Routing Algorithm for Faulty Network-on-Chips

This paper introduces Twist-routing, a new routing algorithm for faulty on-chip networks, which improves Maze-routing, a face-routing based algorithm which uses deflections in routing, and archives full fault coverage and fast packet delivery. To build Twist-routing algorithm, we use bounding circles, which borrows the idea from GOAFR+ routing algorithm for ad-hoc wireless networks. Unlike Maze-routing, whose path length is unbounded even when the optimal path length is fixed, in Twist-routing, the path length is bounded by the cube of the optimal path length. Our evaluations show that Twist-routing algorithm delivers packets up to 35% faster than Maze-routing with a uniform traffic and Erdos-Rényi failure model, when the failure rate and the injection rate vary.

3-D SPIDERGON:3-D TOPOLOGY OF DELAY OPTIMIZATION FOR NETWORKS-ON-CHIP

A 3-D topology architeeture based on Spidergon and its generation method are proposed. Aiming at establishing relationships between the topology architecture and the latency, the 3-D topology latency model based on prototype is proposed, and then the optimization topology structure with minimum latency is determined based on it. Meanwhile, in accordance with the structure, the adaptive routing algorithm is designed. The algorithm sets longitudinal direction priority to adaptively searching the equivalent minimum path between the source nodes and the destination nodes in order to increase network throughput. Simulation shows that in case of approximate saturation network, compared with the same scale 3-D mesh structure, 3-D Spidergon has 17% less latency and 16.7% more network throughput.

三维片上网络拓扑结构研究综述

三维片上网络(three-dimensional network on chip,3D No C)是在三维集成电路(three-dimensional integrated circuit,3D IC)、片上系统(system on chip,So C)和二维片上网络(two-dimensional network on chip,2D No C)的基础上发展起来的,主要解决高集成度芯片通信瓶颈等问题,已引起国内外学术界和产业界的高度重视。3D No C拓扑结构体现了通信节点在芯片中的布局与连接,对三维芯片性能起决定性作用。简介了2D No C、2D No C到3D No C的演变、3D No C的优点与存在的问题以及3D No C解决的关键技术问题,分析了3D No C总体发展状况。三维拓扑结构是3D No C设计中的关键问题之一,重点研究了3D No C拓扑结构的分类方法,从通信角度将3D No C拓扑结构分成9大类,分类论述了3D No C拓扑结构,并分析比较了现有63种拓扑结构各自的特点,最后指出了3D No C拓扑结构的未来研究方向。

带分复用的三维片上网络测试规划研究

三维片上网络(3D No C)中IP核的测试问题日趋突出,测试规划是提高测试效率的有效方法。基于重用No C作为测试存取机制的并行测试方法,针对IP核测试数据传输带宽与TAM带宽不匹配的问题,提出带分复用方法,对有限带宽的TAM进行动态细分,将多核的测试数据共享同一物理TAM实施并行传输,并结合3D No C结构设计二维编码,建立带宽分配和测试顺序模型,采用多种群遗传模拟退火算法,在总功耗、层功耗双重约束下对IP核的带宽分配和测试顺序进行双重优化,提高并行测试效率以获得最短测试时间。算法中针对测试顺序优化设计移位互换杂交策略,并运用精英配对方法加快种群寻优速度,设计求精操作进一步优化测试时间,通过比较、淘汰、替换机制加强种群间交流,增加种群多样性,避免算法陷入局部最优。以ITC'02标准电路作为测试对象,实验结果表明,该方法通过提高带宽利用率,提升了并行测试效率,降低了资源占用,有效地缩短了测试时间。

三维片上网络路由算法的研究

三维集成电路是集成电路发展的一个主要趋势,为了解决大规模三维集成电路的互连问题,三维片上网络应运而生.而三维路由算法决定了每个数据包在传输时所要经历的路径,以及数据包是否能正确地传送到目的地址,是三维片上网络研究的关键技术之一.本文从是否考虑网络流量和拥塞状况的角度,将三维路由算法分为无关路由算法和自适应路由算法,并对目前已提出的三维路由算法的性能进行分析与综述,指出了三维片上网络路由算法的研究方向.

一种面向三维微处理器的新型片上网络拓扑

利用三维集成电路中硅通孔具有延迟短、功耗低的特性,针对10层以上硅片堆叠的三维片上网络,设计了一种新的拓扑结构3DE-Mesh,并通过实验数据的分析,验证了3DE-Mesh的性能和可扩展性.结果表明,3DE-Mesh的性能和可扩展性均满足10层以上硅片堆叠的三维集成电路的要求.

基于Prim初始种群选取优化遗传算法的三维片上网络低功耗映射

针对将计算任务合理地映射到三维片上网络(NoC)的问题,提出了一种基于遗传算法(GA)的改进算法。GA具有快速随机的搜索能力,Prim算法可在加权连通图内得到最小生成树,改进算法结合了两种算法的优势,将计算任务合理地分配到各个网络节点,对于优化三维片上网络功耗和散热等问题具有很高的效率。通过仿真实验,对所提出的基于Prim算法的改进GA与基本GA的3D NoC映射算法进行了对比,仿真结果显示,基于Prim算法的改进GA平均功耗更低,从总体趋势来看,处理单元数量的增加与功耗降低幅度成正相关,在101个处理单元情况下,平均功耗比基本GA降低32%。

利用拥塞信息片上网络自适应容错路由算法

3D片上网络(NoC)可以为高性能的片上系统(SoC)提供有效可扩展的通信架构。针对3D NOC架构的可靠性易受运行错误影响的问题,提出一种近邻拥塞信息感知的自适应容错路由算法(FT-DyXYZ),根据邻近拥堵信息来平衡网络中的负载,利用自适应路由算法选择轻拥堵无故障的最短路径进行数据传输。该算法无需路由表、冗余信息、路径和错误的全局信息,大大降低了计算开销。在不同负载模式和错误链接率的情况下进行实验,结果表明,相比平面自适应路由算法,FT-DyXYZ在延迟、饱和注入率和投递率等性能方面具有显著优势。

特定应用片上网络的研究综述

特大规模集成电路技术的飞速发展,使得把大量的知识产权(Intellectual Property,IP)核集成到单一的芯片上形成的片上系统成为了今后微电子发展的主流趋势。片上系统面临着许多设计和制造问题,片上网络为解决片上系统的这些问题提供一种行之有效的方案。当前及今后的片上系统都主要面向特定应用或特定应用类,因此,片上网络也是面向特定应用的片上网络,对特定应用片上系统面临的问题、特定片上网络的提出、发展、和主要研究内容进行综述。

Reliability-aware mapping and links voltage assignment for energy-efficient networks-on-chip

As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC architecture and assign voltage levels for each link,such that the communication energy is minimized under constraints of bandwidth and reliability.The design space is explored using tabu search.In order to select optimal voltage level for the links,an energy-efficiency driven heuristic algorithm is proposed to perform energy/reliability trade-off by exploiting communication slack.Experimental results show that the ordinary energy optimization techniques ignoring the influence of voltage on fault rates could lead to drastically decreased communication reliability of NoCs,and the proposed approach can produce reliable and energy-efficient implementations.

VELAN: Variable Energy Aware Sense Amplifier Link for Asynchronous Network on Chip

A real time multiprocessor chip paradigm is also called a Network-on-Chip (NoC) which offers a promising architecture for future systems-on-chips. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy and latency than its intended design during heavy traffic condition. Variable Energy aware sense amplifier Link for Asynchronous NoC (VELAN) is designed in this research to eliminate the difficulty, which is the combination of Variable DTSA circuitry (V-DTSA) and Transceiver. The V-DTSA circuitry has following components such as bootable DTSA (B-DTSA) and bootable clock gating DTSA (BCG-DTSA), Graph theory based Traffic Estimator (GTE) and controller. Depending upon the traffic rate, the controller activates necessary DTSA modules and transfers information to the receiver. The proposed VELAN design is evaluated on TSMC 90 nm technology, showing 6.157 Gb/s data rate, 0.27 w total link power and 354 ps latency for single stage operation.

FSM Based DFS Link for Network on Chip

As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMCCMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work.