Three-Dimensional Cooperative Localization via Space-Air-Ground Integrated Networks

The space-air-ground integrated network(SAGIN)combines the superiority of the satellite,aerial,and ground communications,which is envisioned to provide high-precision positioning ability as well as seamless connectivity in the 5G and Beyond 5G(B5G)systems.In this paper,we propose a three-dimensional SAGIN localization scheme for ground agents utilizing multi-source information from satellites,base stations and unmanned aerial vehicles(UAVs).Based on the designed scheme,we derive the positioning performance bound and establish a distributed maximum likelihood algorithm to jointly estimate the positions and clock offsets of ground agents.Simulation results demonstrate the validity of the SAGIN localization scheme and reveal the effects of the number of satellites,the number of base stations,the number of UAVs and clock noise on positioning performance.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

Speeding up carbon nanotube integrated circuits through three-dimensional architecture

Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.

Ultrahigh-power electrochemical double-layer capacitors based on structurally integrated 3D carbon tube arrays

The rational design of electrodes is the key to achieving ultrahigh-power performance in electrochemical energy storage devices.Recently,we have constructed well-organized and integrated three-dimensional(3D)carbon tube(CT)grids(3D-CTGs)using a 3D porous anodic aluminum oxide template-assisted method as electrodes of electrical double-layer capacitors(EDLCs),showing excellent frequency response performance.The unique design warrants fast ion migration channels,excellent electronic conductivity,and good structural stability.This study achieved one of the highest carbon-based ultrahigh-power EDLCs with the 3D-CTG electrodes,resulting in ultrahigh power of 437 and 1708 W·cm−3 with aqueous and organic electrolytes,respectively.Capacitors constructed with these electrodes would have important application prospects in the ultrahigh-power output.The rational design and fabrication of the 3D-CTGs electrodes have demonstrated their capability to build capacitors with ultrahighpower performance and open up new possibilities for applications requiring high-power output.

A 12-Bit 1-Gsample/s Nyquist Current-Steering DAC in 0.35 µm CMOS for Wireless Transmitter

The present work deals with 12-bit Nyquist current-steering CMOS digital-to-analog converter (DAC) which is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for the proposed DAC leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3-D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1-GSample/s frequency. Simulation results show that the spurious- free-dynamic-range (SFDR) in Nyquist rate is better than 64 dB for sampling frequency up to 1-GSample/s. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. The chip has been processed in a standard 0.35 μm CMOS technology. Active area of chip is 1.37 mm2.

Three-dimensional interconnected Ni（Fe）OxHy nanosheets on stainless steel mesh as a robust integrated oxygen evolution electrode

The development of an electrocatalyst based on abundant elements for the oxygen evolution reaction （OER） is important for water splitting associated with renewable energy sources. In this study, we develop an interconnected Ni（Fe）OxHy nanosheet array on a stainless steel mesh （SSNNi） as an integrated OER electrode, without using any polymer binder. Benefiting from the well- defined three-dimensional （3D） architecture with highly exposed surface area, intimate contact between the active species and conductive substrate improved electron and mass transport capacity, facilitated electrolyte penetration, and improved mechanical stability. The SSNNi electrode also has excellent OER performance, including low overpotential, a small Tafel slope, and long-term durability in the alkaline electrolyte, making it one of the most promising OER electrodes developed.

Development of a viable 3D integrated circuit technology

Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.

电流型CMOS脉冲D触发器设计

该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。

Efficient Hierarchical Algorithm for Mixed Mode Placement in Three Dimensional Integrated Circuit Chip Designs

Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.

Resistive switching memory for high density storage and computing

The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.

Integrating MEMS and ICs

The majority of microelectromechanical system(MEMS)devices must be combined with integrated circuits(ICs)for operation in larger electronic systems.While MEMS transducers sense or control physical,optical or chemical quantities,ICs typically provide functionalities related to the signals of these transducers,such as analog-to-digital conversion,amplification,filtering and information processing as well as communication between the MEMS transducer and the outside world.Thus,the vast majority of commercial MEMS products,such as accelerometers,gyroscopes and micro-mirror arrays,are integrated and packaged together with ICs.There are a variety of possible methods of integrating and packaging MEMS and IC components,and the technology of choice strongly depends on the device,the field of application and the commercial requirements.In this review paper,traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed.These include approaches based on the hybrid integration of multiple chips(multi-chip solutions)as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques.These are important technological building blocks for the‘More-Than-Moore’paradigm described in the International Technology Roadmap for Semiconductors.In this paper,the various approaches are categorized in a coherent manner,their merits are discussed,and suitable application areas and implementations are critically investigated.The implications of the different MEMS and IC integration approaches for packaging,testing and final system costs are reviewed.

Circuit modeling and performance analysis of SWCNT bundle 3D interconnects

Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.

三维微电子学综述

三维微电子学主要研究三维集成电路的设计与制造。文章讨论了三维集成电路的概念、发明思想、结构、优点、制造及其挑战和应用等。三维微电子技术必将成为未来发展的新兴技术。

三维结构可重构阵列在线自诊断与容错方法

目前传统的可重构阵列容错方法一般需要控制器来完成重构控制,容错重构控制算法复杂,资源利用率不高,因此提出一种面向三维结构的可重构阵列分布式自主容错方法。系统由相同的电子细胞以三维结构组成,每个细胞能进行故障定位且实现故障自修复;采用基于广度优先布线算法的重布线机制在三维细胞阵列中寻找最近冗余细胞;冗余细胞按比例均匀分布在三维阵列中,可增加容错重构控制过程的灵活性,缩短重构时间。以4位并行乘法器电路为例,对可重构阵列的功能和容错能力进行验证,实验结果表明该方法能够实现三维可重构阵列分布式自主故障诊断与修复,可容错多次故障且容错重构时间短,冗余资源利用率高。

Sourcing the merits of 3D integrated air cathodes for highperformance Zn-air batteries by bubble pump consumption chronoamperometry

Zn-air batteries(ZABs)as a potential energy conversion system suffer from low power density(typically≤200 mW·cm^(−2)).Recently,three-dimensional(3D)integrated air cathodes have demonstrated promising performance over traditional twodimensional(2D)plane ones,which is ascribed to enriched active sites and enhanced diffusion,but without experimental evidence.Herein,we applied a bubble pump consumption chronoamperometry(BPCC)method to quantitatively identify the gas diffusion coefficient(D)and effective catalytic sites density(ρEC)of the integrated air cathodes for ZABs.Furthermore,the D andρEC values can instruct consequent optimization on the growth of Co embedded N-doped carbon nanotubes(CoNCNTs)on carbon fiber paper(CFP)and aerophilicity tuning,giving 4 times D and 1.3 timesρEC over the conventional 2D Pt/C-CFP counterparts.As a result,using the CoNCNTs with half-wave potential of merely 0.78 V vs.RHE(Pt/C:0.89 V vs.RHE),the superaerophilic CoNCNTs-CFP cathode-based ZABs exhibited a superior peak power density of 245 mW·cm^(−2) over traditional 2D Pt/C-CFP counterparts,breaking the threshold of 200 mW·cm^(−2).This work reveals the intrinsic feature of the 3D integrated air cathodes by yielding exact D andρEC values,and demonstrates the feasibility of BPCC method for the optimization of integrated electrodes,bypassing trial-and-error strategy.

二维和三维集成电路的热阻计算

聚焦芯片功耗密度、水平互连焦耳热和垂直互连焦耳热三种温升因素,构造二维和三维集成电路的热阻分析模型,基于2003年国际半导体技术发展路线图(2003-ITRS),计算二维和三维集成电路的热阻和温升参数,给出热阻二维图和温升三维图。分析结论为热阻参数是严重影响二维和三维集成电路发展的瓶颈。

基于链式的信号转移冗余TSV方案

三维集成电路(3D IC)带来了诸多的益处,譬如高带宽,低功耗,外形尺寸小。基于硅通孔的三维集成得到了行业的广泛采用。然而,硅通孔的制造过程引入了新的缺陷机制。一个失效的硅通孔会使整个芯片失效,会极大地增加成本。增加冗余硅通孔修复失效硅通孔可能是最有效的提高良率的方法,但是却带来了面积成本。提出了一种基于链式的信号转移冗余方案,输入端从下一分组选择信号硅通孔传输信号。在基于概率模型下,提出的冗余结构良率可以达到99%,同时可以减少冗余TSV的数目。

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。

三维涡流计算中最少变量数边界积分方程的一个注记

本文回顾了求解三维电磁场涡流问题的数值计算方法 ,其中最少变量数边界积分方程法 (BoundaryIn tegralEquationsofMinimumOrderMethod)具有很多优点 .但提出该方法的论文以及后续论文中的边界积分方程中存在一些错误 ,本文给出了边界积分方程的极限推导过程 ,改正了这些错误 .

Advanced Process and Electron Device Technology

This article reviews advanced process and electron device technology of integrated circuits,including recent featuring progress and potential solutions for future development.In 5 years,for pushing the performance of fin field-effect transistors(FinFET)to its limitations,several processes and device boosters are provided.Then,the three-dimensional(3 D)integration schemes with alternative materials and device architectures will pave paths for future technology evolution.Finally,it could be concluded that Moore’s law will undoubtedly continue in the next 15 years.