The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received dig...The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers （RDLs）, TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient （$11） and signal transmission coefficient （$21） are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance （RLGC） elements of the TSV channel are iterated from scattering （S）-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure （HFSS） simulation software by Ansoft.展开更多
We present an accurate through silicon via （TSV） thermal mechanical stress analytical model which is verified by using finite element method （FEM）. The results show only a very small error. By using the proposed a...We present an accurate through silicon via （TSV） thermal mechanical stress analytical model which is verified by using finite element method （FEM）. The results show only a very small error. By using the proposed analytical model, we also study the impacts of the TSV radius size, the thickness, the material of Cu diffusion barrier, and liner on the stress. It is found that the liner can absorb the stress effectively induced by coefficient of thermal expansion mismatch. The stress decreases with the increase of liner thickness. Benzocyclobutene （BCB） as a liner material is better than SiO2. However, the Cu diffusion barrier has little effect on the stress. The stress with a smaller TSV has a smaller value. Based on the analytical model, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed FEM simulations. The analytic solutions of stress of two TSVs and three TSVs have high precision against the finite element result.展开更多
The barrier/seed layer is a key issue in Through Silicon Via （TSV） technology for 3-D integration. Sputtering is an important deposition method for via metallization in semiconductor process. However, due to the lim...The barrier/seed layer is a key issue in Through Silicon Via （TSV） technology for 3-D integration. Sputtering is an important deposition method for via metallization in semiconductor process. However, due to the limitation of sputtering and a ＂scallop＂ profile inside vias, poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper, the effects of several sputter parameters （DC power, Ar pressure, deposition time, and substrate temperature） on thin film coverage for TSV applications are investigated. Robust TSVs with aspect ratio 5 ： 1 were obtained with optimized magnetron sputter parameters. In addition, the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.展开更多
A ball grid array （BGA） package based on Si interposer with through silicon via （TSV） was de- signed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA w...A ball grid array （BGA） package based on Si interposer with through silicon via （TSV） was de- signed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling （FEM）. The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA pack- age includes a 100 ~m thick Si interposer, which has redistribution copper traces on both sides. Through vias with 25 to 40 ~m diameter were fabricated on the Si interposer using deep reactive ion etching （DRIE）, plasma enhanced chemical vapor deposition （PECVD）, copper electroplating and chemical mechanical pol- ishing （CMP）, etc. TSV in the designed interposer is used as electrical interconnections and cooling chan- nels. 5 mm by 5 mm and 10 mm by 10 mm thermal chips were assembled on the Si interposer.展开更多
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical ...Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.61204044)
文摘The through silicon via （TSV） technology has proven to be the critical enabler to realize a three-dimensional （3D） gigscale system with higher performance but shorter interconnect length. However, the received digital signal after trans- mission through a TSV channel, composed of redistribution layers （RDLs）, TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflec- tion of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient （$11） and signal transmission coefficient （$21） are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance （RLGC） elements of the TSV channel are iterated from scattering （S）-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure （HFSS） simulation software by Ansoft.
基金supported by the National Natural Science Foundation of China(Grant No.61334003)the Kunshan Innovation Institute of Xidian University
文摘We present an accurate through silicon via （TSV） thermal mechanical stress analytical model which is verified by using finite element method （FEM）. The results show only a very small error. By using the proposed analytical model, we also study the impacts of the TSV radius size, the thickness, the material of Cu diffusion barrier, and liner on the stress. It is found that the liner can absorb the stress effectively induced by coefficient of thermal expansion mismatch. The stress decreases with the increase of liner thickness. Benzocyclobutene （BCB） as a liner material is better than SiO2. However, the Cu diffusion barrier has little effect on the stress. The stress with a smaller TSV has a smaller value. Based on the analytical model, we explore and validate the linear superposition principle of stress tensors and demonstrate the accuracy of this method against detailed FEM simulations. The analytic solutions of stress of two TSVs and three TSVs have high precision against the finite element result.
基金supported by the National Natural Science Foundation of China (No. 61274111)he National Science & Technology Major Project of China (No. 2011ZX02709)
文摘The barrier/seed layer is a key issue in Through Silicon Via （TSV） technology for 3-D integration. Sputtering is an important deposition method for via metallization in semiconductor process. However, due to the limitation of sputtering and a ＂scallop＂ profile inside vias, poor step coverage of the barrier/seed layer always occurs in the via metallization process. In this paper, the effects of several sputter parameters （DC power, Ar pressure, deposition time, and substrate temperature） on thin film coverage for TSV applications are investigated. Robust TSVs with aspect ratio 5 ： 1 were obtained with optimized magnetron sputter parameters. In addition, the influences of different sputter parameters are compared and the conclusion could be used as a guideline to select appropriate parameter sets.
基金Supported by the National S&T Major Project (No. 2009ZX02038)the National High-Tech Research and Development (863) Program of China (No. 2009AA04321)supported by Cisco Systems Inc
文摘A ball grid array （BGA） package based on Si interposer with through silicon via （TSV） was de- signed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling （FEM）. The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA pack- age includes a 100 ~m thick Si interposer, which has redistribution copper traces on both sides. Through vias with 25 to 40 ~m diameter were fabricated on the Si interposer using deep reactive ion etching （DRIE）, plasma enhanced chemical vapor deposition （PECVD）, copper electroplating and chemical mechanical pol- ishing （CMP）, etc. TSV in the designed interposer is used as electrical interconnections and cooling chan- nels. 5 mm by 5 mm and 10 mm by 10 mm thermal chips were assembled on the Si interposer.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61131001,61322405,61204044,61376039,and 61334003)
文摘Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
