Adaptive blind gain correction of time-interleaved ADCs forwide-band communication applications

High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.

SPLIT-ADC BASED DIGITAL BACKGROUND CALIBRATION FOR TIME-INTERLEAVED ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.

A Timing Skew Calibration Scheme in Time-Interleaved ADC

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.

Capacitor self-calibration technique used in time-interleaved successive approximation ADC

A capacitor self-calibration circuit used in a successive approximation analog-to-digital converter （SA-ADC） is presented. This capacitor self-calibration circuit can calibrate erroneous data and work with the ADC by adding an additional clock period. This circuit is used in a 10 bit 32 Msample/s time-interleaved SA- ADC. The chip is implemented with Chart 0. 25 μm 2. 5 V process and totally occupies an area of 1.4 mm× 1.3 mm. After calibration, the simulated signal-to-noise ratio （SNR） is 59. 586 1 dB and the spurious-free dynamic range （SFDR） is 70. 246 dB at 32 MHz. The measured signal-to-noise and distortion ratio （SINAD） is 44. 82 dB and the SFDR is 63. 760 4 dB when the ADC samples a 5.8 MHz sinusoid wave.

系统效能视角下基于改进ADC法的研究生导师能力多维度矩阵构建研究

导师作为研究生培养过程中的第一责任人,其能力高低直接影响研究生的培养质量。文章基于“五位一体”理念提出的“导研、导学、导言、导行、导心”,将导师能力细化为个人能力、课堂教学能力、日常学术指导能力、研究生的学术成果和研究生非学术成果五大部分,应用结构分析法(Availability Dependability Capability,ADC)的可用性、可靠性和指导能力的概念,构建相应的研究生导师能力多维度矩阵,综合全面地反映导师的能力,为进一步提高研究生培养质量提供参考。

基于ADC和AHP的舰载双波段雷达作战效能评估

针对舰载双波段雷达作战效能评估问题,提出一种基于ADC和AHP的作战效能评估方法。首先,建立了适用于舰载双波段雷达特点的ADC模型,给出了各因子的具体评估过程。然后,通过AHP给出了能力因子各指标权重系数的计算方法。最后以某舰载双波段雷达为例,给出了模型的应用实例。该模型可操作性强,能准确评估舰载双波段雷达作战效能。

基于粗细量化并行与TDC混合的CMOS图像传感器列级ADC设计方法

针对传统单斜式模数转换器(Analog-to-Digital Converter,ADC)和串行两步式ADC在面向大面阵CMOS(Complementary Metal Oxide Semiconductor)图像传感器读出过程中的速度瓶颈问题,本文提出了一种用于高速CMOS图像传感器的全并行ADC设计方法.该方法基于时间共享和时间压缩思想,将细量化时间提前到粗量化时间段内,解决了传统方法的时间冗余问题;同时采用插入式时间差值TDC(Time-to-Digital Converter),实现了全局低频时钟下的快速转换机制.本文基于55-nm 1P4M CMOS工艺对所提方法完成了详细电路设计和全面测试验证,在模拟电压3.3 V,数字电压1.2 V,时钟频率250 MHz,输入电压1.2~2.7 V的情况下,将行时间压缩至825 ns,ADC的微分非线性和积分非线性分别为+0.6/-0.6LSB和+1.6/-1.2LSB,信噪失真比(Signal-to-Noise-and-DistortionRatio,SNDR)为68.271 dB,有效位数(Effective Numbers Of Bits,ENOB)达到11.0489 bit,列不一致性低于0.05%.相比现有的先进ADC,本文提出的方法在保证低功耗、高精度的同时,ADC转换速率提高了87.1%以上,为高速高精度CMOS图像传感器的读出与量化提供了一定的理论支撑.

面向高帧率CMOS图像传感器的12位列级全差分SAR/SS ADC设计

针对高帧率CMOS图像传感器的应用需求,提出一种结合逐次逼近型(Successive Approximation Register,SAR)和单斜坡(Single Slope,SS)结构的混合型模拟数字转换器(Analog to Digital Converter,ADC)。该ADC的分辨率为12位,其中SAR ADC实现高6位量化,SS ADC实现低6位量化。该ADC采用了全差分结构消除采样开关的固定失调并减少非线性误差,同时在SAR ADC中采用了异步逻辑电路进一步缩短转换周期。采用110 nm 1P4M CMOS工艺对该电路进行了设计和版图实现,后仿真结果表明,在20 MHz的时钟下,转换周期仅为3.3μs,无杂散动态范围为77.12 dB,信噪失真比为67.38 dB,有效位数为10.90位。

用于GEM-TPC探测器读出芯片的10 bit20 MSPS SAR ADC设计

随着大面积气体电子倍增器——时间投影室探测器的不断发展,其对读出电子学的密度和集成度要求越来越高。基于180 nm的CMOS工艺设计完成了一款10 bit、20 MSPS的逐次逼近寄存器型模数转换器原型芯片。利用该芯片结合模拟前端模块和数字信号处理器,可实现全数字化的前端读出专用集成电路用于GEM-TPC的读出。该ADC主要由DAC模块、动态比较器模块、异步时钟生成模块和SAR逻辑模块构成。仿真结果表明,输入信号频率为1.836 MHz时,ENOB为8.61 bit,内核功耗约为3.3 mW/Ch。

高精度低功耗噪声整形SAR ADC设计

针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。

一种具有1~128倍可变增益放大器的低功耗Sigma⁃Delta ADC

为满足传感器应用的低功耗需求,设计并实现了一种低功耗Sigma⁃Delta模数转换器(ADC)芯片。该ADC采用一阶全差分开关电容Sigma⁃Delta调制器,且集成了可编程增益放大器(PGA)和Bandgap;使用1.5 bit量化结构,相较于1 bit量化结构减小了3 dB的量化误差;使用优化的反馈电路,减小了电容失配引入的误差;PGA采用轨到轨的运放电路拓扑,增大了整个芯片的电压适应范围。基于180 nm CMOS工艺对该ADC进行了设计和流片。测试结果表明:该Sigma⁃Delta ADC在采样频率512 kHz、过采样率(OSR)为256时,峰值信噪谐波失真比(SNDR)和有效位数(ENOB)分别为75.29 dB和12.21 bit,芯片功耗仅为0.92 mW。芯片能在2.3~5.5 V宽电源电压范围内正常工作,可实现最大128 V/V的增益。适用于小型传感器的信号测量应用,可以满足小型传感器低功耗、高精度的需求。

稀土Ce变质对ADC12铝合金组织及力学性能的影响

采用光学显微镜、扫描电镜、拉伸试验机及布氏硬度计研究了稀土Ce改性处理对ADC12铝合金微观组织及力学性能的影响。结果表明:当加入质量分数为0.6%的稀土Ce时,组织中粗大的初生α-Al相变得圆整、细小且分布均匀,共晶Si相由针片状变为颗粒状。稀土Ce与合金中的Al元素发生共晶反应生成Al11Ce3等金属间化合物,在扫描电镜下化合物形状为长条针状,并呈亮白色。添加质量分数为0.6%Ce有效提高了合金的屈服强度、抗拉强度和伸长率,分别达到171.72、260.37 MPa和4.1%,与未添加Ce元素的合金相比分别提升了33.83%、48.69%和155%,与此同时,合金的布氏硬度也达到峰值,为88 HB。

应用于高速图像传感器的高线性度Latch ADC

针对高速应用设备对CMOS图像传感器高速、高线性度的要求,本文在传统SS ADC(Single Slope ADC,单斜模数转换器)的基础上,实现了一款应用于图像传感器的Latch ADC,工作频率达到了600 MHz。Latch ADC可以多列像素共用一个Gray Code计数器,并通过Latch结构快速锁定和存储数据,实现了SS ADC中Counter和SRAM的功能。本文采用110 nm工艺,实现了一种高速12位Latch ADC。经过仿真验证,本文的Latch ADC具有高线性度,每次转换的周期为7.094μs,平均功率为180.3μW,转换功耗为1.279 nJ.

一种高精度流水线ADC系统设计与建模方法

针对传统模数转换器(analog to digital convertor,ADC)设计复杂度高、仿真迭代时间长的问题,提出了一种高精度ADC系统设计与建模方法。该方法以10 bit 50 MHz流水线ADC为例,首先选取分离采样架构,进行电路的s域变换理论分析;其次对电路中各种非理想噪声的表达式进行精确推导,根据系统中的运放功耗指标进行参数优化;最后分别在MATLAB和Cadence软件中建立模型,进行100点蒙特卡洛仿真。仿真结果表明,在TSMC 180 nm工艺失配下,该流水线ADC有效位数达到9.70 bit,无杂散动态范围维持在76 dB附近,微分非线性在0.3 LSB以内,积分非线性在0.5 LSB以内,核心功耗在8 mW,该分析方法在保证流水线ADC优异性能的同时,大幅提高了设计效率。

稀土Ce变质铸造ADC12铝合金的组织及性能

通过添加稀土Ce的方式对ADC12铝合金进行了变质处理,采用显微组织观察、拉伸试验、断口形貌观察等手段研究了0~0.9%Ce对ADC12铝合金组织和力学性能的影响。结果表明:稀土Ce对ADC12铝合金有较好的变质效果。随着Ce添加量的增加,ADC12合金组织中α-Al相面积分数先升高后降低,合金的抗拉强度和伸长率先升高后降低。Ce添加量0.5%的合金中α-Al相面积分数达到最大值40.2%,其抗拉强度和伸长率也达到最大值,分别为258.2 MPa和3.5%,与未变质的ADC12合金相比,分别提高了37.7%和94.4%。

A 14-bit 200-MS/s time-interleaved ADC with sample-time error calibration

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.

A 10-bit 100-Msps low power time-interleaved ADC using OTA sharing

A high performance 10-bit 100-MS/s two-channel time-interleaved pipelined ADC is designed for intermediate frequency 3G receivers,and OTA is shared among the channels for low power dissipation.Offset mismatch, gain mismatch and time skew mismatch are overcome by OTA sharing,increasing the accuracy of each channel and global passive sampling respectively.The linearity deterioration caused by the charge injection of the output switch and the crosstalk of the off-switch capacitor is removed by modifying the clock signal arrangement.The total power consumption of the presented ADC is 70 mW from a 3.3-V power supply.Fabricated in a 180-nm CMOS process,the core of the prototype occupies an area of 2.5×1.5 mm;,achieving more than 70-dB spurious-free dynamic range and over 56-dB signal-to-noise distortion ratio over the Nyquist input band at 100-MHz sampling frequency.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit,18-MSPS(million samples per second)flash-assisted successive-approximation-register(SAR)analog-to-digital converter(ADC)utilizing hybrid synchronous and asynchronous(HYSAS)timing control logic based on an on-chip delay-locked loop(DLL).The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter(CDAC)than the synchronous and asynchronous SAR ADC.Therefore,the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent.In addition,the fore-ground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter(FIR-BPF)based least-mean-square(LMS)algorithm in an off-chip FPGA(field programmable gate array).Fabricated in 40-nm CMOS process,the proto-type ADC achieves 94.02-dB spurious-free dynamic range(SFDR),and 75.98-dB signal-to-noise-and-distortion ratio(SNDR)for a 2.88-MHz input under 18-MSPS sampling rate.

10 bit高速低功耗SAR ADC设计

基于TSMC40 nm工艺,提出一种高速低功耗逐次逼近型模数转换器。设计电路采用全差分结构,基于vcm-based电容拆分技术解决先进工艺下难以设计精准VCM电平和复杂逻辑的问题,采用double-tail动态比较器实现高速和低功耗,采用TSPC触发器设计SAR逻辑进一步提高速度和降低功耗,采用异步时序,通过环路自身产生比较器时钟,不需要外接时钟信号,降低设计复杂度。在150 MHz采样频率,1.1 V电源电压,奈奎斯特的输入频率下,对该设计进行仿真,仿真结果表明,SAR ADC的ENOB=9.93 bit,SNDR=61.6 dB,SFDR=78.6 dB。

ADC12铝合金高速铣削前刀面磨损机理研究

为了深入研究ADC12铝合金高速铣削中刀具前刀面磨损行为,采用细晶粒硬质合金刀片进行铣削试验,研究了不同切削速度和切削长度下的切削力变化规律以及对刀具磨损的影响,提出两种前刀面黏结程度评价方法,通过刀具磨损形貌观察及表面化学元素分析,探讨了前刀面的磨损形式,深入剖析了黏结磨损机理。结果表明:切削速度为600m/min时,刀具前刀面黏结最为严重,Al元素含量约为67.61%,这与该速度下切削力较大有关;采用黏结面积法发现,切削速度为600m/min时的刀具前刀面黏结面积同样达到最大,约为0.01286mm^(2);在刀具和工件材料接触区域,由于热—力耦合冲击产生黏结磨损,并在磨粒磨损共同作用下出现月牙洼磨损。