This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical ca...This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.展开更多
The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timi...The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.展开更多
在基于功能仿真进行集成电路低功耗设计和研究中,往往需要通过获取电路节点的翻转信息来评估设计电路的功耗并指导相应的优化工作,论文采用PLI(programming Language Interface)编程来扩展仿真工具的功能直接获取设计电路中各个节点的...在基于功能仿真进行集成电路低功耗设计和研究中,往往需要通过获取电路节点的翻转信息来评估设计电路的功耗并指导相应的优化工作,论文采用PLI(programming Language Interface)编程来扩展仿真工具的功能直接获取设计电路中各个节点的工作状态,实现在仿真过程中节点翻转信息的提取,结果表明该方案不仅具有很大的灵活性而且对仿真效率的影响也最小。展开更多
无论氢在电子器件内部以何种形式(H2分子、H原子或H+离子)存在,均会对电子器件电离损伤产生作用,进而影响器件的抗辐照能力。本文深入研究了氢气和空气气氛条件下1 Me V电子辐照栅控横向PNP(GLPNP)型双极晶体管的辐射损伤缺陷演化行为...无论氢在电子器件内部以何种形式(H2分子、H原子或H+离子)存在,均会对电子器件电离损伤产生作用,进而影响器件的抗辐照能力。本文深入研究了氢气和空气气氛条件下1 Me V电子辐照栅控横向PNP(GLPNP)型双极晶体管的辐射损伤缺陷演化行为。利用Keithley 4200SCS半导体参数测试仪对不同气氛下辐照过程中晶体管进行在线原位电性能参数测试,研究晶体管电性能退化与电子辐照注量和氢气深度之间的关系;基于栅扫技术(GS)和深能级瞬态谱技术(DLTS),研究双极晶体管中氢诱导电离损伤缺陷演化的基本特征。研究表明,与空气气氛相比,氢气气氛下电子辐照导致GLPNP的基极电流增加显著,而集电极电流明显降低,产生更多的氧化物电荷和界面态,这些现象均说明氢气加剧双极晶体管的电离辐射损伤。展开更多
文摘This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.
文摘The development and the revolution of nanotechnology require more and effective methods to accurately estimating the timing analysis for any CMOS transistor level circuit. Many researches attempted to resolve the timing analysis, but the best method found till the moment is the Static Timing Analysis (STA). It is considered the best solution because of its accuracy and fast run time. Transistor level models are mandatory required for the best estimating methods, since these take into consideration all analysis scenarios to overcome problems of multiple-input switching, false paths and high stacks that are found in classic CMOS gates. In this paper, transistor level graph model is proposed to describe the behavior of CMOS circuits under predictive Nanotechnology SPICE parameters. This model represents the transistor in the CMOS circuit as nodes in the graph regardless of its positions in the gates to accurately estimating the timing analysis rather than inaccurate estimating which caused by the false paths at the gate level. Accurate static timing analysis is estimated using the model proposed in this paper. Building on the proposed model and the graph theory concepts, new algorithms are proposed and simulated to compute transistor timing analysis using RC model. Simulation results show the validity of the proposed graph model and its algorithms by using predictive Nano-Technology SPICE parameters for the tested technology. An important and effective extension has been achieved in this paper for a one that was published in international conference.
文摘在基于功能仿真进行集成电路低功耗设计和研究中,往往需要通过获取电路节点的翻转信息来评估设计电路的功耗并指导相应的优化工作,论文采用PLI(programming Language Interface)编程来扩展仿真工具的功能直接获取设计电路中各个节点的工作状态,实现在仿真过程中节点翻转信息的提取,结果表明该方案不仅具有很大的灵活性而且对仿真效率的影响也最小。
文摘无论氢在电子器件内部以何种形式(H2分子、H原子或H+离子)存在,均会对电子器件电离损伤产生作用,进而影响器件的抗辐照能力。本文深入研究了氢气和空气气氛条件下1 Me V电子辐照栅控横向PNP(GLPNP)型双极晶体管的辐射损伤缺陷演化行为。利用Keithley 4200SCS半导体参数测试仪对不同气氛下辐照过程中晶体管进行在线原位电性能参数测试,研究晶体管电性能退化与电子辐照注量和氢气深度之间的关系;基于栅扫技术(GS)和深能级瞬态谱技术(DLTS),研究双极晶体管中氢诱导电离损伤缺陷演化的基本特征。研究表明,与空气气氛相比,氢气气氛下电子辐照导致GLPNP的基极电流增加显著,而集电极电流明显降低,产生更多的氧化物电荷和界面态,这些现象均说明氢气加剧双极晶体管的电离辐射损伤。
