Influence of trap-assisted tunneling on trap-assisted tunneling current in double gate tunnel field-effect transistor

Trap-assisted tunneling（TAT） has attracted more and more attention, because it seriously affects the sub-threshold characteristic of tunnel field-effect transistor（TFET）. In this paper, we assess subthreshold performance of double gate TFET（DG-TFET） through a band-to-band tunneling（BTBT） model, including phonon-assisted scattering and acoustic surface phonons scattering. Interface state density profile（D_（it）） and the trap level are included in the simulation to analyze their effects on TAT current and the mechanism of gate leakage current.

Reverse gate leakage mechanism of AlGaN/GaN HEMTs with Au-free gate

The reverse gate leakage mechanism of W-gate and Ti N-gate AlGaN/GaN high-electron-mobility transistors(HEMTs)with N2plasma surface treatment is investigated using current–voltage(I–V)and capacitance–voltage(C–V)characteristics and theoretical calculation analysis.It is found that the main reverse gate leakage mechanism of both devices is the trapassisted tunneling(TAT)mechanism in the entire reverse bias region(-30 V to 0 V).It is also found that the reverse gate leakage current of the W-gate Al GaN/GaN HEMTs is smaller than that of the TiN gate at high reverse gate bias voltage.Moreover,the activation energies of the extracted W-gate and Ti N-gate AlGaN/GaN HEMTs are 0.0551 e V–0.127 eV and0.112 eV–0.201 eV,respectively.

Highly efficient flexible perovskite solar cells with vacuum-assisted low-temperature annealed SnO2 electron transport layer

The demand for lightweight, flexible, and high-performance portable power sources urgently requires high-efficiency and stable flexible solar cells. In the case of perovskite solar cells(PSCs), most of the common electron transport layer(ETL) needs to be annealed for improving the optoelectronic properties,while conventional flexible substrates could barely stand the high temperature. Herein, a vacuumassisted annealing SnO_(2) ETL at low temperature(100℃) is utilized in flexible PSCs and achieved high efficiency of 20.14%. Meanwhile, the open-circuit voltage(V_(oc)) increases from 1.07 V to 1.14 V. The flexible PSCs also show robust bending stability with 86.8% of the initial efficiency is retained after 1000 bending cycles at a bending radius of 5 mm. X-ray photoelectron spectroscopy(XPS), atomic force microscopy(AFM), and contact angle measurements show that the density of oxygen vacancies, the surface roughness of the SnO_(2) layer, and film hydrophobicity are significantly increased, respectively. These improvements could be due to the oxygen-deficient environment in a vacuum chamber, and the rapid evaporation of solvents. The proposed vacuum-assisted low-temperature annealing method not only improves the efficiency of flexible PSCs but is also compatible and promising in the large-scale commercialization of flexible PSCs.

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10^(18) cm^(-3) and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.