A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potentia...A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.展开更多
We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the phy...We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.展开更多
Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap ch...Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.展开更多
Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Co...Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.展开更多
The surface flashover of epoxy resin(EP) composites is a pivotal problem in the field of highvoltage insulation.The regulation of the interface between the filler and matrix is an effective means to suppress flashover...The surface flashover of epoxy resin(EP) composites is a pivotal problem in the field of highvoltage insulation.The regulation of the interface between the filler and matrix is an effective means to suppress flashover.In this work,nano ZnO was fluorinated and grafted using lowtemperature plasma technology,and the fluorinated filler was doped into EP to study the DC surface flashover performance of the composite.The results show that plasma fluorination can effectively inhibit the agglomeration by grafting –CFxgroups onto the surface of nano-ZnO particles.The fluorine-containing groups at the interface provide higher charge binding traps and enhance the insulation strength at the interface.At the same time,the interface bond cooperation caused by plasma treatment also promoted the accelerating effect of nano ZnO on charge dissipation.The two effects synergistically improve the surface flashover performance of epoxy composites.When the concentration of fluorinated ZnO filler is 20%,the flashover voltage has the highest increase,which is 31.52% higher than that of pure EP.In addition,fluorinated ZnO can effectively reduce the dielectric constant and dielectric loss of epoxy composites.The interface interaction mechanism was further analyzed using molecular dynamics simulation and density functional theory simulation.展开更多
A novel rare earth complex of terbium ion with 2-benzoylbenzoic acid and 1, 10-phenathroline (Tb(o-BBA)3 (phen), o-BBA-2-benzoylbenzoic acid, phen = 1, 10-phenathroline) was used as an electroluminescent materia...A novel rare earth complex of terbium ion with 2-benzoylbenzoic acid and 1, 10-phenathroline (Tb(o-BBA)3 (phen), o-BBA-2-benzoylbenzoic acid, phen = 1, 10-phenathroline) was used as an electroluminescent material for the first time. The Tb complex was blended with poly(N-vinylcarbazole) (PVK) in different weight ratios and spinn to coated into films (noted as PVK :Tb films). The photoluminescence (PL) properties of films were investigated and the optimum weight ratio between PVK and Tb(o-BBA)3(phen) was found to be 3:1. Monolayer devices with the structure ITO/PVK: Tb/AI were fabricated and emitted green light, which was characteristic of Tb^3+ emission. The results show that mecha- nisms for PL and EL are different. The PL is considered to be caused because of energy transfer and direct excitation to the Tb(o-BBA)3(phen) molecule, while EL is mainly on charging trapping.展开更多
In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the block...In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase (P/E) speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.展开更多
Because of the discrete charge storage mechanism, charge trapping memory(CTM) technique is a good candidate for aerospace and military missions. The total ionization dose(TID) effects on CTM cells with Al2O3/HfO2/...Because of the discrete charge storage mechanism, charge trapping memory(CTM) technique is a good candidate for aerospace and military missions. The total ionization dose(TID) effects on CTM cells with Al2O3/HfO2/Al2O3(AHA) high-k gate stack structure under in-situ 10 keV x-rays are studied. The C-V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation,thereby inducing the shift of flat band voltage(V(fb)). The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.展开更多
This paper investigates the effects of gamma-ray irradiation on the Shallow-Trench Isolation (STI) leakage currents in 180-nm complementary metal oxide semiconductor technology. No hump effect in the subthreshold re...This paper investigates the effects of gamma-ray irradiation on the Shallow-Trench Isolation (STI) leakage currents in 180-nm complementary metal oxide semiconductor technology. No hump effect in the subthreshold region is observed after irradiation, which is considered to be due to the thin STI corner oxide thickness. A negative substrate bias could effectively suppress the STI leakage, but it also impairs the device characteristics. The three-dimensional simulation is introduced to understand the impact of substrate bias, Moreover, we propose a simple method for extracting the best substrate bias value, which not only eliminates the STI leakage but also has the least impact on the device characteristics.展开更多
Deep submicron n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with shallow trench isolation (STI) are exposed to ionizing dose radiation under different bias conditions. The total ionizing...Deep submicron n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with shallow trench isolation (STI) are exposed to ionizing dose radiation under different bias conditions. The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case (ON bias) for the transistors are discussed. The high electric fields at the corners are partly responsible for the subthreshold hump effect. Charge trapped in the isolation oxide, particularly at the Si/SiO2 interface along the sidewalls of the trench oxide creates a leakage path, which becomes a dominant contributor to the offstate drain-to-source leakage current in the NMOSFET. Non-uniform charge distribution is introduced into a threedimensional (3D) simulation. Good agreement between experimental and simulation results is demonstrated. We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.展开更多
A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor (MOS) structur...A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor (MOS) structure. In this model, the influences of interface trap charge (ITC) at the Si-SiO2 interface and fixed oxide charge (FOC) in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.展开更多
Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we obser...Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.展开更多
In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals (PDAs) on the integrity of an Al2O3/Si3N4/SiOz/Si memory gate stack. The flat...In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals (PDAs) on the integrity of an Al2O3/Si3N4/SiOz/Si memory gate stack. The flat-band voltage (Vfb) turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase (P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.展开更多
The HfO2-based ferroelectric field effect transistors(FeFET)have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits.This article systematically ...The HfO2-based ferroelectric field effect transistors(FeFET)have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits.This article systematically investigates the transient response of negative capacitance(NC)fin field-effect transistors(FinFETs)through two kinds of self-built test schemes.By comparing the results with those of conventional FinFETs,we experimentally demonstrate that the on-current of the NC FinFET is not degraded in the MHz frequency domain.Further test results in the higher frequency domain show that the on-state current of the prepared NC FinFET increases with the decreasing gate pulse width at pulse widths below 100 ns and is consistently greater(about 80%with NC NMOS)than the on-state current of the conventional transistor,indicating the great potential of the NC FET for future high-frequency applications.展开更多
This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping w...This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping was independent of the current density in devices using fluorescent material as the emitting molecule while this process was exactly opposite when phosphorescent material was used. The triplet-triplet annihilation and dissociation of excitons into free charge carriers was considered to contribute to the decrease in phosphorescent emission under high electric fields. Moreover, the fluorescent dye molecule with a lower energy gap and ionized potential than the host emitter was observed to facilitate the carrier trapping mechanism, and it would produce photon emission.展开更多
Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured...Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.展开更多
A composition-modulated (HfO2)x(Al2O3)1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory de...A composition-modulated (HfO2)x(Al2O3)1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated (HfO2)x(Al2O3)l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.展开更多
Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 (HTH) as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures w...Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 (HTH) as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 (next to blocking oxide) serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the fiat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate fiat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.展开更多
In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consider...In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.展开更多
We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random ...We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.展开更多
基金Project supported by the National Natural Science Foundation of China(No.61376106)the University Natural Science Research Key Project of Anhui Province(No.KJ2016A169)the Introduced Talents Project of Anhui Science and Technology University
文摘A two-dimensional analytical model of double-gate(DG) tunneling field-effect transistors(TFETs) with interface trapped charges is proposed in this paper. The influence of the channel mobile charges on the potential profile is also taken into account in order to improve the accuracy of the models. On the basis of potential profile,the electric field is derived and the expression for the drain current is obtained by integrating the BTBT generation rate. The model can be used to study the impact of interface trapped charges on the surface potential, the shortest tunneling length, the drain current and the threshold voltage for varying interface trapped charge densities, length of damaged region as well as the structural parameters of the DG TFET and can also be utilized to design the charge trapped memory devices based on TFET. The biggest advantage of this model is that it is more accurate,and in its expression there are no fitting parameters with small calculating amount. Very good agreements for both the potential, drain current and threshold voltage are observed between the model calculations and the simulated results.
基金Project supported by the National Natural Science Foundation of China(Grant No.92264104)。
文摘We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.
基金the National Natural Science Foundation of China(Grant Nos.12105340,12035019,and12075290)the Youth Innovation Promotion Association of the Chinese Academy of Sciences(Grant No.2020412)。
文摘Heavy ion irradiation effects on charge trapping memory(CTM)capacitors with TiN/Al_(2)O_(3)/HfO_(2)/Al_(2)O_(3)/HfO_(2)/SiO_(2)/p-Si structure have been investigated.The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance-voltage(C-V)characteristics.The C-V curves shift towards the negative direction after swift heavy ion irradiation,due to the net positive charges accumulating in the trapping layer.The memory window decreases with the increase of ion fluence at high voltage,which results from heavy ion-induced structural damage in the blocking layer.The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams.The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.
基金Project supported by the National Natural Science Foundation of China (Grant No.61874029)。
文摘Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.
基金supported by Beijing Natural Science Foundation (No. 3222057)National Natural Science Foundation of China (Nos. 52277147 and 52007065)。
文摘The surface flashover of epoxy resin(EP) composites is a pivotal problem in the field of highvoltage insulation.The regulation of the interface between the filler and matrix is an effective means to suppress flashover.In this work,nano ZnO was fluorinated and grafted using lowtemperature plasma technology,and the fluorinated filler was doped into EP to study the DC surface flashover performance of the composite.The results show that plasma fluorination can effectively inhibit the agglomeration by grafting –CFxgroups onto the surface of nano-ZnO particles.The fluorine-containing groups at the interface provide higher charge binding traps and enhance the insulation strength at the interface.At the same time,the interface bond cooperation caused by plasma treatment also promoted the accelerating effect of nano ZnO on charge dissipation.The two effects synergistically improve the surface flashover performance of epoxy composites.When the concentration of fluorinated ZnO filler is 20%,the flashover voltage has the highest increase,which is 31.52% higher than that of pure EP.In addition,fluorinated ZnO can effectively reduce the dielectric constant and dielectric loss of epoxy composites.The interface interaction mechanism was further analyzed using molecular dynamics simulation and density functional theory simulation.
文摘A novel rare earth complex of terbium ion with 2-benzoylbenzoic acid and 1, 10-phenathroline (Tb(o-BBA)3 (phen), o-BBA-2-benzoylbenzoic acid, phen = 1, 10-phenathroline) was used as an electroluminescent material for the first time. The Tb complex was blended with poly(N-vinylcarbazole) (PVK) in different weight ratios and spinn to coated into films (noted as PVK :Tb films). The photoluminescence (PL) properties of films were investigated and the optimum weight ratio between PVK and Tb(o-BBA)3(phen) was found to be 3:1. Monolayer devices with the structure ITO/PVK: Tb/AI were fabricated and emitted green light, which was characteristic of Tb^3+ emission. The results show that mecha- nisms for PL and EL are different. The PL is considered to be caused because of energy transfer and direct excitation to the Tb(o-BBA)3(phen) molecule, while EL is mainly on charging trapping.
基金supported partially by the National Basic Research Program of China (Grant No. 2010CB934204)the National Natural Science Foundation of China (Grant No. 60825403)+1 种基金the Director’s Fund of Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS)the National Science and Technology Major Project of China (Grant No. 2009ZX02023-005)
文摘In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase (P/E) speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.
基金Supported by the National Natural Science Foundation of China under Grant No 616340084the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant No 2014101+1 种基金the International Cooperation Project of Chinese Academy of Sciencesthe Austrian-Chinese Cooperative R&D Projects under Grant No 172511KYSB20150006
文摘Because of the discrete charge storage mechanism, charge trapping memory(CTM) technique is a good candidate for aerospace and military missions. The total ionization dose(TID) effects on CTM cells with Al2O3/HfO2/Al2O3(AHA) high-k gate stack structure under in-situ 10 keV x-rays are studied. The C-V characteristics at different radiation doses demonstrate that charge stored in the device continues to be leaked away during the irradiation,thereby inducing the shift of flat band voltage(V(fb)). The dc memory window shows insignificant changes, suggesting the existence of good P/E ability. Furthermore, the physical mechanisms of TID induced radiation damages in AHA-based CTM are analyzed.
文摘This paper investigates the effects of gamma-ray irradiation on the Shallow-Trench Isolation (STI) leakage currents in 180-nm complementary metal oxide semiconductor technology. No hump effect in the subthreshold region is observed after irradiation, which is considered to be due to the thin STI corner oxide thickness. A negative substrate bias could effectively suppress the STI leakage, but it also impairs the device characteristics. The three-dimensional simulation is introduced to understand the impact of substrate bias, Moreover, we propose a simple method for extracting the best substrate bias value, which not only eliminates the STI leakage but also has the least impact on the device characteristics.
文摘Deep submicron n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with shallow trench isolation (STI) are exposed to ionizing dose radiation under different bias conditions. The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case (ON bias) for the transistors are discussed. The high electric fields at the corners are partly responsible for the subthreshold hump effect. Charge trapped in the isolation oxide, particularly at the Si/SiO2 interface along the sidewalls of the trench oxide creates a leakage path, which becomes a dominant contributor to the offstate drain-to-source leakage current in the NMOSFET. Non-uniform charge distribution is introduced into a threedimensional (3D) simulation. Good agreement between experimental and simulation results is demonstrated. We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.
基金Project supported by the National Natural Science Foundation of China (Grant No. 61076055)the Program for Innovative Research Team of Zhejiang Normal University of China (Grant No. 2007XCXTD-5)the Open Program of Surface Physics Laboratory of Fudan University, China (Grant No. FDSKL2011-04)
文摘A model based on analysis of the self-consistent Poisson-Schrodinger equation is proposed to investigate the tunneling current of electrons in the inversion layer of a p-type metal-oxide-semiconductor (MOS) structure. In this model, the influences of interface trap charge (ITC) at the Si-SiO2 interface and fixed oxide charge (FOC) in the oxide region are taken into account, and one-band effective mass approximation is used. The tunneling probability is obtained by employing the transfer matrix method. Further, the effects of in-plane momentum on the quantization in the electron motion perpendicular to the Si-SiO2 interface of a MOS device are investigated. Theoretical simulation results indicate that both ITC and FOC have great influence on the tunneling current through a MOS structure when their densities are larger than l012 cm 2, which results from the great change of bound electrons near the Si-SiO2 interface and the oxide region. Therefore, for real ultrathin MOS structures with ITC and FOC, this model can give a more accurate description for the tunneling current in the inversion layer.
文摘Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.
基金Project supported in part by the National Basic Research Program of China(Grant Nos.2010CB934200 and 2011CBA00600)the National Natural Science Foundation of China(Grant Nos.61176073 and 61176080)the Director’s Fund of the Institute of Microelectronics,Chinese Academy of Sciences
文摘In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals (PDAs) on the integrity of an Al2O3/Si3N4/SiOz/Si memory gate stack. The flat-band voltage (Vfb) turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase (P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.
基金This project was supported in part by the Science and Technology program of Beijing Municipal Science and Technology Commission under grant Z201100006820084,in part by the National Natural Science Foundation of China(NSFC)under grants 92064003,61904194,91964202 and 61874135,in part by the Youth Innovation Promotion Association,Chinese Academy of Sciences under grants Y9YQ01R004 and Y2020037,in part by the Opening Project of Key Laboratory of Microelectronic Devices and Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences under grants E0YS01X001 and E0290X03.
文摘The HfO2-based ferroelectric field effect transistors(FeFET)have been widely studied for their ability in breaking the Boltzmann limit and the potential to be applied to low-power circuits.This article systematically investigates the transient response of negative capacitance(NC)fin field-effect transistors(FinFETs)through two kinds of self-built test schemes.By comparing the results with those of conventional FinFETs,we experimentally demonstrate that the on-current of the NC FinFET is not degraded in the MHz frequency domain.Further test results in the higher frequency domain show that the on-state current of the prepared NC FinFET increases with the decreasing gate pulse width at pulse widths below 100 ns and is consistently greater(about 80%with NC NMOS)than the on-state current of the conventional transistor,indicating the great potential of the NC FET for future high-frequency applications.
基金Project supported by the Key Project of Shanghai Education Committee (Grant No. 08ZZ42)Science and Technology Commission of Shanghai Municipal (Grant Nos. 08PJ14053,08DZ1140702 and 08520511200)
文摘This paper utilizes multilayer organic light-emitting diodes with a thin layer of dye molecules to study the mech- anism of charge trapping under different electric regimes. It demonstrates that the carrier trapping was independent of the current density in devices using fluorescent material as the emitting molecule while this process was exactly opposite when phosphorescent material was used. The triplet-triplet annihilation and dissociation of excitons into free charge carriers was considered to contribute to the decrease in phosphorescent emission under high electric fields. Moreover, the fluorescent dye molecule with a lower energy gap and ionized potential than the host emitter was observed to facilitate the carrier trapping mechanism, and it would produce photon emission.
基金supported by the National Natural Science Foundation of China(Grant No.61106080)the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2013ZX02305)
文摘Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage(C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope(XPS) and transmission electron microscope(TEM)measurements. In addition, Rutherford back scattering(RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer.
基金supported by the Science and Technology Research Key Project of Education Department of Henan, China (Grant No. 13A140021)the National Natural Science Foundation of China (Grant Nos. 50972054 and 61176124)+1 种基金the National Basic Research Program of China (Grant No. 2010CB934201)the State Key Program for Science and Technology of China (Grant No. 2009ZX02039-004)
文摘A composition-modulated (HfO2)x(Al2O3)1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated (HfO2)x(Al2O3)l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.
基金Supported by the National Basic Research Program of China under Grant No 2011CBA00602the National Key Scientific and Technological Project under Grant No 2013ZX01032001-001-003
文摘Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 (HTH) as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 (next to blocking oxide) serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the fiat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate fiat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.
基金supported by the National Natural Science Foundation of China(Grant Nos.61404005,61421005,and 91434201)
文摘In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.
基金supported by the National Natural Science Foundation of China(Grant Nos.613760966,1327813,61404126 and 11947115)the Natural Science Foundation of Henan Province under(Grant No.202300410444)Foreign Experts Program of Ministry of Science and Technology in China(Grant No.G2021026027L)。
文摘We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO_(2) interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 10^(12) cm^(–2) and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.