An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction （SJ） MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.

A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

A new ultralow gate–drain charge(Q_(GD)) 4 H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures(DS-MOS): one is the grounded split gate(SG), the other is the P+shielding region(PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance(C_(GD)) into the gate–source capacitance(C_(GS)) and drain–source capacitance(C_(DS)) in series.Thus the C_(GD) is reduced and the proposed DS-MOS obtains ultralow Q_(GD). Compared with the double-trench MOSFET(DT-MOS)and the conventional trench MOSFET(CT-MOS), the proposed DS-MOS decreases the Q_(GD) by 85% and 81%, respectively.Moreover, the figure of merit(FOM), defined as the product of specific on-resistance(R_(on, sp)) and Q_(GD)(R_(on, sp)Q_(GD)), is reduced by 84% and 81%, respectively.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate(SG), and p-type pillar(ppillar) surrounded thick oxide shielding region(GSDP-TMOS) is investigated by Silvaco TCAD simulations. The sourceconnected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge(Q_(gd,sp)) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage(BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance(Ron,sp) becomes smaller.In the end, comparing with the bottom p~+ shielded trench MOSFET(GP-TMOS), the Baliga figure of merit(BFOM,BV~2/R_(on,sp)) is increased by 169.6%, and the high-frequency figure of merit(HF-FOM, R_(on,sp) × Q_(gd,sp)) is improved by310%, respectively.

一种抗辐射Trench型N 30 V MOSFET器件设计

由于Trench结构在降低元胞单元尺寸、提升沟道密度和消除JFET区电阻等方面的优势,Trench型MOSFET已广泛应用于低压产品领域。在研究抗辐射机理和抗辐射加固技术的基础上,设计了一款新型抗辐射Trench型N30VMOSFET器件。实验结果显示,产品击穿电压典型值达42V,特征导通电阻为51mΩ·mm^(2)。在^(60)Co γ射线100krad(Si)条件下,器件阈值电压漂移仅为-0.3V,漏源漏电流从34nA仅上升到60nA。采用能量为2006MeV、硅中射程为116μm、线性能量传输(LET)值为75.4MeV·cm^(2)/mg的^(118)Ta离子垂直入射该器件,未发生单粒子事件。

Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate

An ultralow specific on-resistance （Ron,sp） trench metal-oxide-semiconductor field effect transistor （MOSFET） with an improved off-state breakdown voltage （BV） is proposed. It features a U-shaped gate around the drift region and an oxide trench inserted in the drift region （UG MOSFET）. In the on-state, the U-shaped gate induces a high density electron accumulation layer along its sidewall, which provides a low-resistance current path from the source to the drain, realizing an ultralow Ron,sp. The value of Ron,sp is almost independent of the drift doping concentration, and thus the UG MOSFET breaks through the contradiction relationship between R p and the off-state BV. Moreover, the oxide trench folds the drift region, enabling the UG MOSFET to support a high BV with a shortened cell pitch. The UG MOSFET achieves an Ron,sp of 2 mΩ·cm^2 and an improved BV of 216 V, superior to the best existing state-of-the-art transistors at the same BV level

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)structure with side-wall p-type pillar(p-pillar)and wrap n-type pillar(n-pillar)in the n-drain was investigated by utilizing Silvaco TCAD simulations.The optimized structure mainly includes a p+buried region,a light n-type current spreading layer(CSL),a p-type pillar region,and a wrapping n-type pillar region at the right and bottom of the p-pillar.The improved structure is named as SNPPT-MOS.The side-wall p-pillar region could better relieve the high electric field around the p+shielding region and the gate oxide in the off-state mode.The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance(Ron,sp).As a result,the SNPPT-MOS structure exhibits that the figure of merit(Fo M)related to the breakdown voltage(V_(BR))and Ron,sp(V_(BR)^2R_(on,sp))of the SNPPT-MOS is improved by 44.5%,in comparison to that of the conventional trench gate SJ MOSFET(full-SJ-MOS).In addition,the SNPPT-MOS structure achieves a much fasterwitching speed than the full-SJ-MOS,and the result indicates an appreciable reduction in the switching energy loss.

A 4H-SiC semi-super-junction shielded trench MOSFET: p-pillar is grounded to optimize the electric field characteristics

A 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor(UMOSFET)with semi-super-junction shiel-ded structure(SS-UMOS)is proposed and compared with conventional trench MOSFET(CT-UMOS)in this work.The advantage of the proposed structure is given by comprehensive study of the mechanism of the local semi-super-junction structure at the bottom of the trench MOSFET.In particular,the influence of the bias condition of the p-pillar at the bottom of the trench on the static and dynamic performances of the device is compared and revealed.The on-resistance of SS-UMOS with grounded(G)and ungrounded(NG)p-pillar is reduced by 52%(G)and 71%(NG)compared to CT-UMOS,respectively.Additionally,gate ox-ide in the GSS-UMOS is fully protected by the p-shield layer as well as semi-super-junction structure under the trench and p-base regions.Thus,a reduced electric-field of 2 MV/cm can be achieved at the corner of the p-shield layer.However,the quasi-intrinsic protective layer cannot be formed in NGSS-UMOS due to the charge storage effect in the floating p-pillar,resulting in a large electric field of 2.7 MV/cm at the gate oxide layer.Moreover,the total switching loss of GSS-UMOS is 1.95 mJ/cm2 and is reduced by 18%compared with CT-UMOS.On the contrary,the NGSS-UMOS has the slowest overall switching speed due to the weakened shielding effect of the p-pillar and the largest gate-to-drain capacitance among the three.The proposed GSS-UMOS plays an important role in high-voltage and high-frequency applications,and will provide a valuable idea for device design and circuit applications.

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal–oxide–semiconductor field-effect transistor(MOSFET)(UMOSFET)fitted with a super-junction(SJ)shielded region.The modified structure is composed of two n-type conductive pillars,three p-type conductive pillars,an oxide trench under the gate,and a light n-type current spreading layer(NCSL)under the p-body.The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer,thus improving the specific on-resistance(R_(on,sp)).There are three p-type pillars in the modified structure,with the p-type pillars on both sides playing the same role.The p-type conductive pillars relieve the electric field(E-field)in the corner of the trench bottom.Two-dimensional simulation(silvaco TCAD)indicates that Ron,sp of the modified structure,and breakdown voltage(V_(BR))are improved by 22.2%and 21.1%respectively,while the maximum figure of merit(FOM=V_(BR)^(2)/R_(on,sp)) is improved by 79.0%.Furthermore,the improved structure achieves a light smaller low gate-to-drain charge(Q_(gd))and when compared with the conventional UMOSFET(conventional-UMOS),it displays great advantages for reducing the switching energy loss.These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance,which also enables the charge carriers to be extracted quickly.In the end,under the condition of the same total charge quantity,the simulation comparison of gate charge and OFF-state characteristics between Gaussdoped structure and uniform-doped structure shows that Gauss-doped structure increases the V_(BR)of the device without degradation of dynamic performance.

DC-DC转换器中功率沟槽MOSFET的优化设计

利用工艺和器件模拟软件TSUPREM-4和MEDICI,研究了工艺参数对DC-DC转换器中的功率沟槽MOSFET的通态电阻Ron、栅-漏电容Cgd的影响以及栅-漏电荷Qgd在开关过程中的变化,指出了在设计和工艺上减小通态电阻Ron和栅-漏电容Cgd,提高器件综合性能的途径。

4H-SiC台阶型沟槽MOSFET器件

介绍了一种4H-SiC台阶型沟槽MOSFET器件。该结构引入了台阶状沟槽,使用TCAD软件对台阶状沟槽的数量、深度、宽度等参数进行了拉偏仿真,确定了最优台阶结构参数。仿真结果表明,与传统的UMOS器件相比,最优台阶结构参数下的台阶状沟槽MOSFET器件关断状态下的栅氧化层尖峰电场减小了12%,FOM值提升了5.1%。提出了形成台阶的一种可行性方案,并给出了实验结果,SEM结果表明,可以通过侧墙生长加湿法腐蚀的方法形成形貌良好的台阶。

一种基于BSIM4的屏蔽栅沟槽MOSFET紧凑型模型

提出了一种基于BSIM4的屏蔽栅沟槽MOSFET紧凑型模型.在直流模型中使用两端电势建立JFET区等效电阻模型,并引入电子扩散区等效电阻,解决了因忽视JFET区源端电势导致的电流存在误差的问题.在电容模型中,漏源电容模型在BSIM4的基础上添加了屏蔽栅-漏等效电容模型,栅漏电容模型将栅漏偏置电压修改为栅极同栅-漂移区重叠区末端节点的电势差.使用泊松方程求解该节点电势,并引入栅氧厚度因子k1、屏蔽栅氧化层厚度因子k2、等效栅-漂移区重叠长度Lovequ和等效屏蔽栅长LSHequ对栅和屏蔽栅的结构进行等效,以简化泊松方程的计算并确保该节点电势曲线的光滑性.使用Verilog-A编写模型程序,搭建实验平台测试屏蔽栅沟槽MOSFET的直流特性、电容特性和开关特性,模型仿真结果与测试数据有较好的拟合,验证了所建模型的有效性.

槽栅型SiC MOSFET器件单粒子响应特性研究

利用TCAD Sentaurus模拟仿真软件,研究分析了三种不同结构的槽栅型1200 V SiC MOSFET单粒子响应特性,器件包括传统单沟槽MOSFET、双沟槽MOSFET和非对称沟槽MOSFET结构。仿真结果表明,双沟槽MOSFET的抗单粒子特性优于其它两种结构器件。通过分析可知,双沟槽MOSFET结构的优越性在于有较深的源极深槽结构,有助于快速收集单粒子碰撞过程产生的载流子,从而缓解大量载流子聚集带来的内部电热集中,相比其它两种结构能有效抑制引起单粒子烧毁的反馈机制。

低比导通电阻P埋层SOI双介质槽MOSFET

提出了一种带P型埋层的新型SOI双介质槽MOSFET。通过在SOI层底部引入P型埋层作为补偿,在耐压优化情况下增加漂移区的浓度,降低了比导通电阻。MEDICI TCAD仿真结果表明:在281V击穿电压下,该结构的比导通电阻为4.6mΩ.cm2,与不带P型埋层的结构相比,在达到同样耐压的情况下,比导通电阻降低了19%。

SGT MOSFET的研究与进展

介绍了SGT MOSFET的研究历史和结构演进,对SGT MOSFET发展过程中出现的各种新结构的结构特点和电学特性做了简要阐述;简要说明了SGT MOSFET在改善器件反向耐压BV和比导通电阻Rsp以及UIS和BV稳定性方面的研究进展;同时列举了SGT MOSFET的一些最新研究成果和需要解决的问题,以及今后的研究发展重点。

基于TCAD技术的碳化硅槽栅MOSFET器件设计

针对碳化硅槽栅MOSFET器件内部寄生二极管的反向恢复特性差的问题,设计了碳化硅槽栅MOSFET器件新结构,通过在碳化硅槽栅MOSFET器件元胞内部集成多晶硅/碳化硅异质结二极管,在不使器件的其他电学特性退化的基础上,改善器件的反向恢复特性。基于TCAD工具——ATLAS二维的半导体工艺与器件仿真软件,对碳化硅槽栅MOSFET器件的I-V特性、击穿特性以及反向恢复特性进行了研究。研究结果表明,与常规的碳化硅槽栅MOSFET器件相比,新结构的反向恢复特性明显改善,反向恢复时间减小了48.8%,反向恢复电荷减小了94.1%,反向峰值电流减小了82.4%。

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。

一种沟槽型SGTMOSFET终端结构

为了在提升终端耐压的同时减少终端的使用面积,基于屏蔽栅沟槽型MOSFET (shielded gate trench MOSFET,简称SGTMOSFET)设计了一种沟槽型终端。通过Sentaurus TCAD软件对终端结构进行仿真,仅改变沟槽和P型环参数,最终使终端的耐压达到了135V,有效终端长度仅为18.5μm。此终端结构适用于中低压领域,且在SGTMOSFET元胞工艺步骤的基础上仅增加了一层掩膜,终端结构工艺和元胞工艺兼容,易于实现。

碳化硅沟槽栅MOSFET技术研究进展

第三代宽禁带半导体碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)具备耐高压、耐高温和低损耗等优点,迅速成为行业的研究热点。文章结合SiC功率MOSFET器件发展历史,探讨了从平面栅技术发展到沟槽栅技术的必要性,介绍了SiC沟槽栅MOSFET结构设计、沟槽刻蚀工艺和沟槽栅氧工艺等核心问题的研究进展与技术挑战,并对未来新型SiC沟槽栅MOSFET技术进行了展望。

屏蔽栅沟槽MOSFET单粒子微剂量效应研究

以屏蔽栅沟槽(SGT)MOSFET为研究对象,研究了重离子诱发的单粒子微剂量效应的现象及物理机理。对不同偏置电压下的30 V SGT MOSFET进行重离子辐照试验,分析了重离子轰击后器件转移特性曲线的变化趋势,揭示单粒子微剂量效应的退化规律。研究发现重离子入射会引起器件的亚阈值电流增大,导致阈值电压负向漂移,且负栅压下器件的亚阈值电压负向漂移更严重。试验结果结合TCAD仿真进一步揭示在栅氧化层侧墙处Si/SiO_(2)界面的带正电的氧化物陷阱电荷是导致器件阈值电压和亚阈值电压等参数退化的主要原因。研究结果可为SGT MOSFET单粒子微剂量效应评估和建模提供指导。

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET （TPMOS） structure based on VD- MOS technology, in which the shallow trench is located at the center of the n- drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only im- proves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.