The strain impact on hole mobility in the GOI tri-gate pFETs is investigated by simulating the strained Ge with quantum confinement from band structure to electro-static distribution as well as the effective mobility....The strain impact on hole mobility in the GOI tri-gate pFETs is investigated by simulating the strained Ge with quantum confinement from band structure to electro-static distribution as well as the effective mobility. Lattice mismatch strain induced by HfO2 warps and reshapes the valence subbands, and reduces the hole effective masses. The maximum value of hole density is observed near the top comers of the channel. The hole density is decreased by the lattice mismatch strain. The phonon scattering rate is degraded by strain, which results in higher hole mobility.展开更多
This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is go...This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.展开更多
Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performanc...Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.展开更多
Combining logical function and memory characteristics of transistors is an ideal strategy for enhancing computational efficiency of transistor devices.Here,we rationally design a tri-gate two-dimensional(2D)ferroelect...Combining logical function and memory characteristics of transistors is an ideal strategy for enhancing computational efficiency of transistor devices.Here,we rationally design a tri-gate two-dimensional(2D)ferroelectric van der Waals heterostructures device based on copper indium thiophosphate(CuInP_(2)S_(6))and few layers tungsten disulfide(WS_(2)),and demonstrate its multi-functional applications in multi-valued state of data,non-volatile storage,and logic operation.By co-regulating the input signals across the tri-gate,we show that the device can switch functions flexibly at a low supply voltage of 6 V,giving rise to an ultra-high current switching ratio of 107 and a low subthreshold swing of 53.9 mV/dec.These findings offer perspectives in designing smart 2D devices with excellent functions based on ferroelectric van der Waals heterostructures.展开更多
Two-dimensional(2D)transition metal dichalcogenides(TMDs)such as molybdenum disulfide(M0S2)have been intensively investigated because of their exclusive physical properties for advaneed electronics and optoelectronics...Two-dimensional(2D)transition metal dichalcogenides(TMDs)such as molybdenum disulfide(M0S2)have been intensively investigated because of their exclusive physical properties for advaneed electronics and optoelectronics.In the present work,we study the M0S2 transistor based on a novel tri-gate device architecture,with dual-gate(Dual-G)in the channel and the buried side-gate(Side-G)for the source/drain regi ons.All gates can be in depe ndently con trolled without in terfere nee.For a MoS2 sheet with a thick ness of 3.6 nm,the Schottky barrier(SB)and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G.Thus,the extri nsic resista nee can be effectively lowered,and a boost of the ON-state cur re nt can be achieved.Mean while,the cha nn el c ontrol remai ns efficient under the Dual-G mode,with an ON-OFF current ratio of 3 x 107 and subthreshold swing of 83 mV/decade.The corresponding band diagram is also discussed to illustrate the device operati on mechanism.This no vel device structure ope ns up a new way toward fabricati on of high-performance devices based on 2D-TMDs.展开更多
文摘The strain impact on hole mobility in the GOI tri-gate pFETs is investigated by simulating the strained Ge with quantum confinement from band structure to electro-static distribution as well as the effective mobility. Lattice mismatch strain induced by HfO2 warps and reshapes the valence subbands, and reduces the hole effective masses. The maximum value of hole density is observed near the top comers of the channel. The hole density is decreased by the lattice mismatch strain. The phonon scattering rate is degraded by strain, which results in higher hole mobility.
文摘This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.
文摘Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.
基金supported by the National Natural Science Foundation of China(No.62104073)the China Postdoctoral Science Foundation(No.2021M691088)+1 种基金the Pearl River Talent Recruitment Program(No.2019ZT08X639)Z.C.W.acknowledges the European Research Executive Agency(Project 101079184-FUNLAYERS).
文摘Combining logical function and memory characteristics of transistors is an ideal strategy for enhancing computational efficiency of transistor devices.Here,we rationally design a tri-gate two-dimensional(2D)ferroelectric van der Waals heterostructures device based on copper indium thiophosphate(CuInP_(2)S_(6))and few layers tungsten disulfide(WS_(2)),and demonstrate its multi-functional applications in multi-valued state of data,non-volatile storage,and logic operation.By co-regulating the input signals across the tri-gate,we show that the device can switch functions flexibly at a low supply voltage of 6 V,giving rise to an ultra-high current switching ratio of 107 and a low subthreshold swing of 53.9 mV/dec.These findings offer perspectives in designing smart 2D devices with excellent functions based on ferroelectric van der Waals heterostructures.
基金This work was supported by the National Key Research and Development Program of China(Nos.2016YFA0203900 and 2018YFA0306101)Shanghai Municipal Science and Technology Commission(No.18JC1410300)Natural Science Foundation of China(No.61874154).
文摘Two-dimensional(2D)transition metal dichalcogenides(TMDs)such as molybdenum disulfide(M0S2)have been intensively investigated because of their exclusive physical properties for advaneed electronics and optoelectronics.In the present work,we study the M0S2 transistor based on a novel tri-gate device architecture,with dual-gate(Dual-G)in the channel and the buried side-gate(Side-G)for the source/drain regi ons.All gates can be in depe ndently con trolled without in terfere nee.For a MoS2 sheet with a thick ness of 3.6 nm,the Schottky barrier(SB)and non-overlapped channel region can be effectively tuned by electrostatically doping the source/drain regions with Side-G.Thus,the extri nsic resista nee can be effectively lowered,and a boost of the ON-state cur re nt can be achieved.Mean while,the cha nn el c ontrol remai ns efficient under the Dual-G mode,with an ON-OFF current ratio of 3 x 107 and subthreshold swing of 83 mV/decade.The corresponding band diagram is also discussed to illustrate the device operati on mechanism.This no vel device structure ope ns up a new way toward fabricati on of high-performance devices based on 2D-TMDs.
