Image segmentation of exfoliated two-dimensional materials by generative adversarial network-based data augmentation

Mechanically cleaved two-dimensional materials are random in size and thickness.Recognizing atomically thin flakes by human experts is inefficient and unsuitable for scalable production.Deep learning algorithms have been adopted as an alternative,nevertheless a major challenge is a lack of sufficient actual training images.Here we report the generation of synthetic two-dimensional materials images using StyleGAN3 to complement the dataset.DeepLabv3Plus network is trained with the synthetic images which reduces overfitting and improves recognition accuracy to over 90%.A semi-supervisory technique for labeling images is introduced to reduce manual efforts.The sharper edges recognized by this method facilitate material stacking with precise edge alignment,which benefits exploring novel properties of layered-material devices that crucially depend on the interlayer twist-angle.This feasible and efficient method allows for the rapid and high-quality manufacturing of atomically thin materials and devices.

Automatic modulation recognition of radiation source signals based on two-dimensional data matrix and improved residual neural network

Automatic modulation recognition(AMR)of radiation source signals is a research focus in the field of cognitive radio.However,the AMR of radiation source signals at low SNRs still faces a great challenge.Therefore,the AMR method of radiation source signals based on two-dimensional data matrix and improved residual neural network is proposed in this paper.First,the time series of the radiation source signals are reconstructed into two-dimensional data matrix,which greatly simplifies the signal preprocessing process.Second,the depthwise convolution and large-size convolutional kernels based residual neural network(DLRNet)is proposed to improve the feature extraction capability of the AMR model.Finally,the model performs feature extraction and classification on the two-dimensional data matrix to obtain the recognition vector that represents the signal modulation type.Theoretical analysis and simulation results show that the AMR method based on two-dimensional data matrix and improved residual network can significantly improve the accuracy of the AMR method.The recognition accuracy of the proposed method maintains a high level greater than 90% even at -14 dB SNR.

Single event effects evaluation on convolution neural network in Xilinx 28 nm system on chip

Convolutional neural networks(CNNs) exhibit excellent performance in the areas of image recognition and object detection, which can enhance the intelligence level of spacecraft. However, in aerospace, energetic particles, such as heavy ions, protons, and alpha particles, can induce single event effects(SEEs) that lead CNNs to malfunction and can significantly impact the reliability of a CNN system. In this paper, the MNIST CNN system was constructed based on a 28 nm systemon-chip(SoC), and then an alpha particle irradiation experiment and fault injection were applied to evaluate the SEE of the CNN system. Various types of soft errors in the CNN system have been detected, and the SEE cross sections have been calculated. Furthermore, the mechanisms behind some soft errors have been explained. This research will provide technical support for the design of radiation-resistant artificial intelligence chips.

Research of Tile Type Transceiver Module Integrating with Two-Dimensional Sum Difference Network

Transceiver module and two-dimensional sum difference network are important components of phased array antenna. In this paper, multilayer printed board is used to integrate millimeter wave multi-channel transceiver circuit and sum difference network. The interconnection between them is realized through RF coaxial vertical transition. At the same time, the heat dissipation design and inter channel shielding design of the module are carried out. The RF and low frequency required by the module are completed through the wiring between and within the dielectric plate layers. Finally, 128 arrays are fabricated and verified by multi-channel passive test. The results show that the type transceiver module integrating with two-dimensional sum difference network has good performance, and 128 channels have excellent amplitude and phase characteristics. The integration technology has the characteristics of lightweight, miniaturization, high integration and low manufacturing cost. It can be widely used in miniaturized phased array antennas.

SIMULATION AND PERFORMANCE ANALYSIS OF NETWORK ON CHIP ARCHITECTURES

The network on chip（NoC）is used as a solution for the communication problems in a complex system on chip（SoC）design.To further enhance performances,the NoC architectures,a high level modeling and an evaluation method based on OPNET are proposed to analyze their performances on different injection rates and traffic patterns.Simulation results for general NoC in terms of the average latency and the throughput are analyzed and used as a guideline to make appropriate choices for a given application.Finally,a MPEG4 decoder is mapped on different NoC architectures.Results prove the effectiveness of the evaluation method.

ARTIFICIAL NEURAL NETWORK MODELLING OF A WOOD CHIP REFINER

1 INTRODUCTIONWood chip refining is the most critical step in mechanical pulping.Commercical experi-ences have been gained for years.Modelling and control of chip refiners,however,pose a challenge mainly because of the stochastic nature of the process.Some attemptshave been made to employ factor analysis technique[1]in the modelling andsimulating of refiner operation[2,3].Strand[2]used common factors as links betweenintrinsic fibre properties and pulp quality.He believed that a qualitative concept onthe physical nature of these common factors could be arrived at,and thus would helpto understand what refining variables need to be controlled or adjusted in order to im-prove pulp quality.However,the linear model used in factor analysis is based on theassumption that the interactions among the system variables are linear,which,ofcourse,is not true in practice.

Pattern recognition in multi-synaptic photonic spiking neural networks based on a DFB-SA chip

Spiking neural networks(SNNs)utilize brain-like spatiotemporal spike encoding for simulating brain functions.Photonic SNN offers an ultrahigh speed and power efficiency platform for implementing high-performance neuromorphic computing.Here,we proposed a multi-synaptic photonic SNN,combining the modified remote supervised learning with delayweight co-training to achieve pattern classification.The impact of multi-synaptic connections and the robustness of the network were investigated through numerical simulations.In addition,the collaborative computing of algorithm and hardware was demonstrated based on a fabricated integrated distributed feedback laser with a saturable absorber(DFB-SA),where 10 different noisy digital patterns were successfully classified.A functional photonic SNN that far exceeds the scale limit of hardware integration was achieved based on time-division multiplexing,demonstrating the capability of hardware-algorithm co-computation.

A PRIORITY-BASED POLLING SCHEDULING ALGORITHM FOR ARBITRATION POLICY IN NETWORK ON CHIP

A solution is imperatively expected to meet the efficient contention resolution schemes for managing simultaneous access requests to the communication resources on the Network on Chip (NoC). Based on the ideas of conflict-free transmission, priority-based service, and dynamic self-adaptation to loading, this paper presents a novel scheduling algorithm for Medium Access Control (MAC) in NoC with the researches of the communication structure features of 2D mesh. The algorithm gives priority to guarantee the Quality of Service (QoS) for local input port as well as dynamic adjustment of the performance of the other ports along with input load change. The theoretical model of this algorithm is established with Markov chain and probability generating function. Mathematical analysis is made on the mean queue length and the mean inquiry cyclic time of the system. Simulated experiments are conducted to test the accuracy of the model. It turns out that the findings from theoretical analysis correspond well with those from simulated experiments. Further more, the analytical findings of the system performance demonstrate that the algorithm enables effectively strengthen the fairness and stability of data transmissions in NoC.

Designs of 3D Mesh and Torus Optical Network-on-Chips:Topology,Optical Router and Routing Module

As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.

Design and simulation of a Torus topology for network on chip

Aiming at the applications of NOC （network on chip） technology in rising scale and complexity on chip systems, a Torus structure and corresponding route algorithm for NOC is proposed. This Torus structure improves traditional Torus topology and redefines the denotations of the routers. Through redefining the router denotations and changing the original router locations, the Torus structure for NOC application is reconstructed. On the basis of this structure, a dead-lock and live-lock free route algorithm is designed according to dimension increase. System C is used to implement this structure and the route algorithm is simulated. In the four different traffic patterns, average, hotspot 13%, hotspot 67% and transpose, the average delay and normalization throughput of this Torus structure are evaluated. Then, the performance of delay and throughput between this Torus and Mesh structure is compared. The results indicate that this Torus structure is more suitable for NOC applications.

New Latency Model for Dynamic Frequency Scaling on Network-on-Chip

Modulating both the clock frequency and supply voltage of the network-on-chip （NoC） during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary to find a tradeoff between power consumption and communication latency. So we propose an analytical latency model which can show us the relationship of them. The proposed model to analyze latency is based on the M/G/1 queuing model, which is suitable for dynamic frequency scaling. The experiment results show that the accuracy of this model is more than 90%.

Efficient stochastic parallel gradient descent training for on-chip optical processor

In recent years,space-division multiplexing(SDM)technology,which involves transmitting data information on multiple parallel channels for efficient capacity scaling,has been widely used in fiber and free-space optical communication sys-tems.To enable flexible data management and cope with the mixing between different channels,the integrated reconfig-urable optical processor is used for optical switching and mitigating the channel crosstalk.However,efficient online train-ing becomes intricate and challenging,particularly when dealing with a significant number of channels.Here we use the stochastic parallel gradient descent(SPGD)algorithm to configure the integrated optical processor,which has less com-putation than the traditional gradient descent(GD)algorithm.We design and fabricate a 6×6 on-chip optical processor on silicon platform to implement optical switching and descrambling assisted by the online training with the SPDG algorithm.Moreover,we apply the on-chip processor configured by the SPGD algorithm to optical communications for optical switching and efficiently mitigating the channel crosstalk in SDM systems.In comparison with the traditional GD al-gorithm,it is found that the SPGD algorithm features better performance especially when the scale of matrix is large,which means it has the potential to optimize large-scale optical matrix computation acceleration chips.

Cluster Based Hierarchical Routing Algorithm for Network on Chip

This paper presents a new logical mechanism called as Cluster Based Hierarchical Routing (CBHR) to improve the efficiency of NoC. This algorithm comprises the following steps: 1) the network is segmented logically into clusters with same size or different sizes;2) algorithms are assigned for internal and global routing;3) routers working functions are modified logically to support local and global communication. The experiments have conducted for CBHR algorithm for two dimensional mesh and torus architectures. The performance of this mechanism is analyzed and compared with other deterministic and adaptive routing algorithms in terms of energy, throughput with different packet injection ratios.

Two-dimensional horizontal visibility graph analysis of human brain aging on gray matter

Characterizing the trajectory of the healthy aging brain and exploring age-related structural changes in the brain can help deepen our understanding of the mechanism of brain aging.Currently,most structural magnetic resonance imaging literature explores brain aging merely from the perspective of morphological features,which cannot fully utilize the grayscale values containing important intrinsic information about brain structure.In this study,we propose the construction of two-dimensional horizontal visibility graphs based on the pixel intensity values of the gray matter slices directly.Normalized network structure entropy(NNSE)is then introduced to quantify the overall heterogeneities of these graphs.The results demonstrate a decrease in the NNSEs of gray matter with age.Compared with the middle-aged and the elderly,the larger values of the NNSE in the younger group may indicate more homogeneous network structures,smaller differences in importance between nodes and thus a more powerful ability to tolerate intrusion.In addition,the hub nodes of different adult age groups are primarily located in the precuneus,cingulate gyrus,superior temporal gyrus,inferior temporal gyrus,parahippocampal gyrus,insula,precentral gyrus and postcentral gyrus.Our study can provide a new perspective for understanding and exploring the structural mechanism of brain aging.

Two-Dimensional Images of Current and Active Power Signals for Elevator Condition Recognition

In this paper, an improved two-dimensional convolution neural network(2DCNN) is proposed to monitor and analyze elevator health, based on the distribution characteristics of elevator time series data in two-dimensional images. The current and effective power signals from an elevator traction machine are collected to generate gray-scale binary images. The improved two-dimensional convolution neural network is used to extract deep features from the images for classification, so as to recognize the elevator working conditions. Furthermore, the oscillation criterion is proposed to describe and analyze the active power oscillations. The current and active power are used to synchronously describe the working condition of the elevator, which can explain the co-occurrence state and potential relationship of elevator data. Based on the improved integration of local features of the time series, the recognition accuracy of the proposed 2DCNN is 97.78%, which is better than that of a one-dimensional convolution neural network. This research can improve the real-time monitoring and visual analysis performance of the elevator maintenance personnel, as well as improve their work efficiency.

An Evaluation of Routing Algorithms in Traffic Engineering and Quality of Service Provision of Network on Chips

Nowadays the number of cores that are integrated into NoC (Network on Chip) systems is steadily increasing, and real application traffic, running in such multi-core environments requires more and more bandwidth. In that sense, NoC architectures should be properly designed so as to provide efficient traffic engineering, as well as QoS support. Routing algorithm choice in conjunction with other parameters, such as network size and topology, traffic features (time and spatial distribution), as well as packet injection rate, packet size, and buffering capability, are all equivalently critical for designing a robust NoC architecture, on the grounds of traffic engineering and QoS provision. In this paper, a thorough numerical investigation is achieved by taking into consideration the criticality of selecting the proper routing algorithm, in conjunction with all the other aforementioned parameters. This is done via implementation of four routing evaluation traffic scenarios varying each parameter either individually, or as a set, thus exhausting all possible combinations, and making compact decisions on proper routing algorithm selection in NoC architectures. It has been shown that the simplicity of a deterministic routing algorithm such as XY, seems to be a reasonable choice, not only for random traffic patterns but also for non-uniform distributed traffic patterns, in terms of delay and throughput for 2D mesh NoC systems.

Designing cost-effective network-on-chip by dual-channel access mechanism

A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.

Design of Efficient Router with Low Power and Low Latency for Network on Chip

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

Application Aware Topology Generation for Surface Wave Networks-on-Chip

The networks-on-chip （NoC） communication has an increasingly larger impact on the system power consumption and performance. Emerging technologies, like surface wave, are believed to have lower transmission latency and power consumption over the conventional wireless NoC. Therefore, this paper studies how to optimize the network performance and power consumption by giving the packet-switching fabric and traffic pattern of each application. Compared with the conventional method of wire-linked, which adds wireless transceivers by using the genetic algorithm （GA）, the proposed maximal declining sorting algorithm （MDSA） can effectively reduce time consumption by as much as 20.4% to 35.6%. We also evaluate the power consumption and configuration time to prove the effective of the proposed algorithm.