Spectroscopic ellipsometry (SE), photocarrier radiometry (PCR) and photoluminescence (PL) techniques were employed to measure the ultra-shallow junction (USJ) wafers. These USJ wafers were prepared by As+ ion implanta...Spectroscopic ellipsometry (SE), photocarrier radiometry (PCR) and photoluminescence (PL) techniques were employed to measure the ultra-shallow junction (USJ) wafers. These USJ wafers were prepared by As+ ion implantation at energies of 0.5-5 keV, at a dose of 1×1015 As+ /cm 2 and spike annealing. Experimentally the damaged layer of the as-implanted wafer and the recrystallization and activation of the post-annealed wafer were evaluated by SE in the spectral range from 0.27 to 20 m. The PCR amplitude decreased monotonically with the increasing implantation energy. The experimental results also showed that the PCR amplitudes of post-annealed USJ wafers were greatly enhanced, compared to the non-implanted and non-annealed substrate wafer. The PL measurements showed the enhanced PCR signals were attributed to the band-edge emissions of silicon. For explaining the PL enhancement, the electronic transport properties of USJ wafers were extracted via multi-wavelength PCR experiment and fitting. The fitted results showed the decreasing surface recombination velocity and the decreasing diffusion coefficient of the implanted layer contributed to the PCR signal enhancement with the decreasing implantation energy. SE, PCR and PL were proven to be non-destructive metrology tools for characterizing ultra-shallow junctions.展开更多
随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(N iS i)金属栅功函数的影响.对具有不同剂...随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(N iS i)金属栅功函数的影响.对具有不同剂量Ge注入的N iS i金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对N iS i金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,N iS i金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.展开更多
针对纳米PMOS器件超浅结工艺面临的硼扩散问题,开展了预非晶化与激光退火和碳共注入结合的超浅结实验,通过透射式电子显微镜(TEM),二次离子质谱(SIMS),扩展电阻法(SRP)等测试对超浅结特性进行评估。结果表明,采用激光退火和碳共注入的...针对纳米PMOS器件超浅结工艺面临的硼扩散问题,开展了预非晶化与激光退火和碳共注入结合的超浅结实验,通过透射式电子显微镜(TEM),二次离子质谱(SIMS),扩展电阻法(SRP)等测试对超浅结特性进行评估。结果表明,采用激光退火和碳共注入的方式可有效抑制硼扩散和减小结深。锗预非晶化后5 ke V,1×10^(15)/cm^2条件下注入的硼在激光退火(波长532 nm、脉冲宽度小于20 ns、能量密度0.25 J/cm^2)中的再扩散量非常小,退火后结深较注入结深仅增加6 nm,但激活率仅为24%。相同的硼掺杂条件下采用碳的共注入,常规快速热退火下的结深较未注碳样品减小49%,而且实现了84%的硼激活率。在单项实验基础上,进一步将预非晶化和碳共注入技术应用于纳米尺度器件制作,实验制备了亚50 nm PMOS器件,器件在Vdd=-1.2 V时的电流开关比大于104,亚阈值斜率为100 m V/dec,漏致势垒降低(DIBL)值为104 m V/V。展开更多
With Shockley＇s approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier （OPA） was realized. The high-performance PJFET devi...With Shockley＇s approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier （OPA） was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz^1/2, and current noise of less than 0.05 pA/Hz^1/2.展开更多
基金supported by the National Natural Science Foundation of China(Grant Nos. 61076090 and 60676058)
文摘Spectroscopic ellipsometry (SE), photocarrier radiometry (PCR) and photoluminescence (PL) techniques were employed to measure the ultra-shallow junction (USJ) wafers. These USJ wafers were prepared by As+ ion implantation at energies of 0.5-5 keV, at a dose of 1×1015 As+ /cm 2 and spike annealing. Experimentally the damaged layer of the as-implanted wafer and the recrystallization and activation of the post-annealed wafer were evaluated by SE in the spectral range from 0.27 to 20 m. The PCR amplitude decreased monotonically with the increasing implantation energy. The experimental results also showed that the PCR amplitudes of post-annealed USJ wafers were greatly enhanced, compared to the non-implanted and non-annealed substrate wafer. The PL measurements showed the enhanced PCR signals were attributed to the band-edge emissions of silicon. For explaining the PL enhancement, the electronic transport properties of USJ wafers were extracted via multi-wavelength PCR experiment and fitting. The fitted results showed the decreasing surface recombination velocity and the decreasing diffusion coefficient of the implanted layer contributed to the PCR signal enhancement with the decreasing implantation energy. SE, PCR and PL were proven to be non-destructive metrology tools for characterizing ultra-shallow junctions.
文摘随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(N iS i)金属栅功函数的影响.对具有不同剂量Ge注入的N iS i金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对N iS i金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,N iS i金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.
文摘针对纳米PMOS器件超浅结工艺面临的硼扩散问题,开展了预非晶化与激光退火和碳共注入结合的超浅结实验,通过透射式电子显微镜(TEM),二次离子质谱(SIMS),扩展电阻法(SRP)等测试对超浅结特性进行评估。结果表明,采用激光退火和碳共注入的方式可有效抑制硼扩散和减小结深。锗预非晶化后5 ke V,1×10^(15)/cm^2条件下注入的硼在激光退火(波长532 nm、脉冲宽度小于20 ns、能量密度0.25 J/cm^2)中的再扩散量非常小,退火后结深较注入结深仅增加6 nm,但激活率仅为24%。相同的硼掺杂条件下采用碳的共注入,常规快速热退火下的结深较未注碳样品减小49%,而且实现了84%的硼激活率。在单项实验基础上,进一步将预非晶化和碳共注入技术应用于纳米尺度器件制作,实验制备了亚50 nm PMOS器件,器件在Vdd=-1.2 V时的电流开关比大于104,亚阈值斜率为100 m V/dec,漏致势垒降低(DIBL)值为104 m V/V。
基金supported by the Innovative Fund of the China Electronics Technology Group Corporation(CETC)(No.GJ0708020).
文摘With Shockley＇s approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier （OPA） was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz^1/2, and current noise of less than 0.05 pA/Hz^1/2.
