This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-pow...This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm^2 and 0.12 mm^2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of （268 kb/s）/（3.0 kb/s）.展开更多
A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is propose...A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver（RX）with an ultra-low-power free-running ring oscillator and a high speed main transmitter（TX）with fast lock-in PLL.A passive wake-up receiver（WuRx）for wake-up function with a high power conversion efficiency（PCE）CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm^2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves ＋3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.展开更多
The recent decade has witnessed an upsurge in the demands of intelligent and simplified Internet of Things(IoT)networks that provide ultra-low-power communication for numerous miniaturized devices.Although the researc...The recent decade has witnessed an upsurge in the demands of intelligent and simplified Internet of Things(IoT)networks that provide ultra-low-power communication for numerous miniaturized devices.Although the research community has paid great attention to wireless protocol designs for these networks,researchers are handicapped by the lack of an energy-efficient software-defined radio(SDR)platform for fast implementation and experimental evaluation.Current SDRs perform well in battery-equipped systems,but fail to support miniaturized IoT devices with stringent hardware and power constraints.This paper takes the first step toward designing an ultra-low-power SDR that satisfies the ultra-low-power or even battery-free requirements of intelligent and simplified IoT networks.To achieve this goal,the core technique is the effective integration ofµW-level backscatter in our SDR to sidestep power-hungry active radio frequency chains.We carefully develop a novel circuit design for efficient energy harvesting and power control,and devise a competent solution for eliminating the harmonic and mirror frequencies caused by backscatter hardware.We evaluate the proposed SDR using different modulation schemes,and it achieves a high data rate of 100 kb/s with power consumption less than 200µW in the active mode and as low as 10µW in the sleep mode.We also conduct a case study of railway inspection using our platform,achieving 1 kb/s battery-free data delivery to the monitoring unmanned aerial vehicle at a distance of 50 m in a real-world environment,and provide two case studies on smart factories and logistic distribution to explore the application of our platform.展开更多
This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the ch...This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.展开更多
A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods...A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.展开更多
基金supported by the National Key Technology Research and Development Program of the Ministry of Science and Technology of China(No.2012BAH20B02)the National High Technology Research and Development Program of China(No.2012AA012301)the National Science and Technology Major Projects of the Ministry of Science and Technology of China(No.2012ZX03004007-002)
文摘This paper presents an ultra-low-power area-efficient non-volatile memory（NVM） in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification（RFID） tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm^2 and 0.12 mm^2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of （268 kb/s）/（3.0 kb/s）.
基金Project supported by the National High-Tech Research and Development Program of China(Nos2008AA010703,2009AA011606)the National Natural Science Foundation of China(No60976023)
文摘A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks（WBANs）in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver（RX）with an ultra-low-power free-running ring oscillator and a high speed main transmitter（TX）with fast lock-in PLL.A passive wake-up receiver（WuRx）for wake-up function with a high power conversion efficiency（PCE）CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm^2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves ＋3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.
基金Project supported by the National Key R&D Program of China(Nos.2020YFB1806606 and 2016YFB1200100)the National Natural Science Foundation of China(No.62071194)。
文摘The recent decade has witnessed an upsurge in the demands of intelligent and simplified Internet of Things(IoT)networks that provide ultra-low-power communication for numerous miniaturized devices.Although the research community has paid great attention to wireless protocol designs for these networks,researchers are handicapped by the lack of an energy-efficient software-defined radio(SDR)platform for fast implementation and experimental evaluation.Current SDRs perform well in battery-equipped systems,but fail to support miniaturized IoT devices with stringent hardware and power constraints.This paper takes the first step toward designing an ultra-low-power SDR that satisfies the ultra-low-power or even battery-free requirements of intelligent and simplified IoT networks.To achieve this goal,the core technique is the effective integration ofµW-level backscatter in our SDR to sidestep power-hungry active radio frequency chains.We carefully develop a novel circuit design for efficient energy harvesting and power control,and devise a competent solution for eliminating the harmonic and mirror frequencies caused by backscatter hardware.We evaluate the proposed SDR using different modulation schemes,and it achieves a high data rate of 100 kb/s with power consumption less than 200µW in the active mode and as low as 10µW in the sleep mode.We also conduct a case study of railway inspection using our platform,achieving 1 kb/s battery-free data delivery to the monitoring unmanned aerial vehicle at a distance of 50 m in a real-world environment,and provide two case studies on smart factories and logistic distribution to explore the application of our platform.
基金Project supported by the National Natural Science Foundation of China(No.60906010).
文摘This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure.Final test results verify the function of the SRAM.The minimal operating voltage of the chip is 350 mV,where the speed is 165 kHz,the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.
文摘A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.
