With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS）...With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.展开更多
A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical p...A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical parameters and the bias condition. The dependence of the RF performance and DC power consumption on physical, material and technological parameters of EFET is also studied. The optimum range of the physical parameters is given which is useful for the design of active device of ultra low power consumption MMIC.展开更多
Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). M...Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.展开更多
A state of the art ultra-low power small sized transceiver design has been proposed.This device consists of four blocks,including a frequency synthesizer(FS),a crystal oscillator(XO),transmitter and receiver attached ...A state of the art ultra-low power small sized transceiver design has been proposed.This device consists of four blocks,including a frequency synthesizer(FS),a crystal oscillator(XO),transmitter and receiver attached with an antenna.It has been seen that wireless information technology and systems have played a vital role in the transformation of society in different aspects of life.Mobile wireless communications including WiMAX/4G have attracted researchers and developers.WiMAX/4G applications need a transceiver that can be used in the worst channel conditions,but with low power consumption and low input voltage at the 5.8 GHz frequency.The proposed transceiver operates on 1.2 V.The operating frequency,noise figure(NF)and receiver gain are 5.8 GHz,4.0 dB and 90 dB respectively.It is a highly compatible transceiver with all the 4G technologies.Implementation details and results have revealed that the proposed transceiver is much more efficient than the previously proposed transceivers in literature.展开更多
CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling metho...CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling methods, but in conventional CMOS devices in ultra deep submicron technology, leakage power becomes the major portion apart of dynamic power. The demerits of the conventional CMOS is less speed and, more leakage, for any digital design PDP is the figure of merit which can be used to determine energy consumed per switching event, hence we designed a NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.展开更多
A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time...A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is -107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is -193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.展开更多
A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits(PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a dis...A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits(PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a distributed architecture, two-tap feedforward equalization(FFE), and a push–pull output stage, exhibiting an estimated differential output swing of 4.0V_(pp). The rms jitter of 2.0 ps is achieved at 50 Gb/s under nonreturnto-zero on–off keying(NRZ-OOK) modulation. The PICs are fabricated on a standard silicon-on-insulator platform and consist of 16 parallel silicon dual-drive Mach–Zehnder modulators on a single chip. The chip-on-board co-packaged Si transmitter is constituted by the multichannel chiplets without any off-chip bias control, which significantly simplifies the system complexity. Experimentally, the open and clear optical eye diagrams of selected channels up to 50 Gb/s OOK with extinction ratios exceeding 3 dB are obtained without any digital signal processing. The power consumption of the Si transmitter with a high integration density featuring a throughput up to 800 Gb/s is only 5.35 p J/bit, indicating a great potential for massively parallel terabit-scale optical interconnects for future hyperscale data centers and high-performance computing systems.展开更多
As a clean and renewable form of energy,photovoltaic(PV)power generation converts solar energy into electrical energy,reducing the consumption of fossil fuels and significantly lowering greenhouse gas emissions.Amidst...As a clean and renewable form of energy,photovoltaic(PV)power generation converts solar energy into electrical energy,reducing the consumption of fossil fuels and significantly lowering greenhouse gas emissions.Amidst the global transition towards cleaner forms of energy,countries all around the world are vigorously developing PV technology.展开更多
Traction power systems(TPSs)play a vital role in the operation of electrified railways.The transformation of conventional railway TPSs to novel structures is not only a trend to promote the development of electrified ...Traction power systems(TPSs)play a vital role in the operation of electrified railways.The transformation of conventional railway TPSs to novel structures is not only a trend to promote the development of electrified railways toward high-efficiency and resilience but also an inevitable requirement to achieve carbon neutrality target.On the basis of sorting out the power supply structures of conventional AC and DC modes,this paper first reviews the characteristics of the existing TPSs,such as weak power supply flexibility and low-energy efficiency.Furthermore,the power supply structures of various TPSs for future electrified railways are described in detail,which satisfy longer distance,low-carbon,high-efficiency,high-reliability and high-quality power supply requirements.Meanwhile,the application prospects of different traction modes are discussed from both technical and economic aspects.Eventually,this paper introduces the research progress of mixed-system electrified railways and traction power supply technologies without catenary system,speculates on the future development trends and challenges of TPSs and predicts that TPSs will be based on the continuous power supply mode,employing power electronic equipment and intelligent information technology to construct a railway comprehensive energy system with renewable energy.展开更多
A BP/CdS heterostructure-based artificial photonic synapse with an ultra-low power consumption is proposed,presenting great potential in high-performance neuromorphic vision systems.
Microwave-assisted mechanical excavation has great application prospects in mines and tunnels,but there are few field experiments on microwave-assisted rock breaking.This paper takes the Sishanling iron mine as the re...Microwave-assisted mechanical excavation has great application prospects in mines and tunnels,but there are few field experiments on microwave-assisted rock breaking.This paper takes the Sishanling iron mine as the research object and adopts the self-developed high-power microwave-induced fracturing test system for hard rock to conduct field experiments of microwave-induced fracturing of iron ore.The heating and reflection evolution characteristics of ore under different microwave parameters(antenna type,power,and working distance)were studied,and the optimal microwave parameters were obtained.Subsequently,the ore was irradiated with the optimal microwave parameters,and the cracking effect of the ore under the action of the high-power open microwave was analyzed.The results show that the reflection coefficient(standing wave ratio)can be rapidly(<5 s)and automatically adjusted below the preset threshold value(1.6)as microwave irradiation is performed.When using a right-angle horn antenna with a working distance of 5 cm,the effect of automatic reflection adjustment reaches the best among other antenna types and working distances.When the working distance is the same,the average temperature of the irradiation surface and the area of the high-temperature area under the action of the two antennas(right-angled and equal-angled horn antenna)are basically the same and decrease with the increase of working distance.The optimal microwave parameters are:a right-angle horn antenna with a working distance of 5 cm.Subsequently,in further experiments,the optimal parameters were used to irradiate for 20 s and 40 s at a microwave power of 60 kW,respectively.The surface damage extended 38 cm×30 cm and 53 cm×30 cm,respectively,and the damage extended to a depth of about 50 cm.The drilling speed was increased by 56.2%and 66.5%,respectively,compared to the case when microwaves were not used.展开更多
Silicon carbide(SiC) power modules play an essential role in the electric vehicle drive system. To improve their performance, reduce their size, and increase production efficiency, this paper proposes a multiple stake...Silicon carbide(SiC) power modules play an essential role in the electric vehicle drive system. To improve their performance, reduce their size, and increase production efficiency, this paper proposes a multiple staked direct bonded copper(DBC) unit based power module packaging method to parallel more chips. This method utilizes mutual inductance cancellation effect to reduce parasitic inductance. Because the conduction area in the new package is doubled, the overall area of power module can be reduced. Entire power module is divided into smaller units to enhance manufacture yield, and improve design freedom. This paper provides a detailed design, analysis and fabrication procedure for the proposed package structure. Additionally, this paper offers several feasible solutions for the connection between power terminals and DBC untis. With the structure, 18dies were paralleled for each phase-leg in a econodual size power module. Both simulation and double pulse test results demonstrate that, compared to conventional layouts, the proposed package method has 74.8% smaller parasitic inductance and 34.9% lower footprint.展开更多
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2009J026
文摘With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.
文摘A model of enhancement mode GaAs MESFET (EFET) for low power consumption and low noise applications has been obtained by using a small signal equivalent circuit whose component values are derived from the physical parameters and the bias condition. The dependence of the RF performance and DC power consumption on physical, material and technological parameters of EFET is also studied. The optimum range of the physical parameters is given which is useful for the design of active device of ultra low power consumption MMIC.
文摘Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.
基金Supported by Young Scientists Fund of the National Natural Science Foundation of China(61201040)
文摘A state of the art ultra-low power small sized transceiver design has been proposed.This device consists of four blocks,including a frequency synthesizer(FS),a crystal oscillator(XO),transmitter and receiver attached with an antenna.It has been seen that wireless information technology and systems have played a vital role in the transformation of society in different aspects of life.Mobile wireless communications including WiMAX/4G have attracted researchers and developers.WiMAX/4G applications need a transceiver that can be used in the worst channel conditions,but with low power consumption and low input voltage at the 5.8 GHz frequency.The proposed transceiver operates on 1.2 V.The operating frequency,noise figure(NF)and receiver gain are 5.8 GHz,4.0 dB and 90 dB respectively.It is a highly compatible transceiver with all the 4G technologies.Implementation details and results have revealed that the proposed transceiver is much more efficient than the previously proposed transceivers in literature.
文摘CMOS devices play a major role in most of the digital design, since CMOS devices have larger density and consume less power. The integrated circuit performance mostly depends on the basic devices and its scaling methods, but in conventional CMOS devices in ultra deep submicron technology, leakage power becomes the major portion apart of dynamic power. The demerits of the conventional CMOS is less speed and, more leakage, for any digital design PDP is the figure of merit which can be used to determine energy consumed per switching event, hence we designed a NOVEL NMOS and PMOS which has superior performance than conventional PMOS and NMOS, the design and performance checked at 90 nm, 180 nm and 45 nm technology and calculate the performance values.
文摘A new design for an ultra-low power, low phase noise differential 10 GHz LC voltage-controlled oscillator (VCO) which is biased in the subthreshold regime, is presented in the 0.18 μm CMOS process, for the first time. The designed circuit topology is an NMOS only cross-coupled LC-tank VCO which has an extra symmetric centre tapped inductor between the source ends of the cross-coupled transistors. Using this inductor leads to an improvement of the phase noise of VCO about 3.5 dB. At the supply voltage of 0.46 V, the output phase noise is -107.8 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 10.53 GHz, so that the dc power consumption is only 0.346 mW. Tuning range is between 10.53 GHz to 11.35 GHz which is 7.5% and the figure of merit is -193.8 dB, which this result shows that this is the first VCO design in the subthreshold regime at this frequency. This VCO can be used for multi-standard wireless LAN communication protocols 802.11a/b/g easily by a frequency division of 2 or 4 respectively.
基金National Key Research and Development Program of China(2021YFB0301000,2020YFB2206100,2022YFB2803700)
文摘A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits(PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a distributed architecture, two-tap feedforward equalization(FFE), and a push–pull output stage, exhibiting an estimated differential output swing of 4.0V_(pp). The rms jitter of 2.0 ps is achieved at 50 Gb/s under nonreturnto-zero on–off keying(NRZ-OOK) modulation. The PICs are fabricated on a standard silicon-on-insulator platform and consist of 16 parallel silicon dual-drive Mach–Zehnder modulators on a single chip. The chip-on-board co-packaged Si transmitter is constituted by the multichannel chiplets without any off-chip bias control, which significantly simplifies the system complexity. Experimentally, the open and clear optical eye diagrams of selected channels up to 50 Gb/s OOK with extinction ratios exceeding 3 dB are obtained without any digital signal processing. The power consumption of the Si transmitter with a high integration density featuring a throughput up to 800 Gb/s is only 5.35 p J/bit, indicating a great potential for massively parallel terabit-scale optical interconnects for future hyperscale data centers and high-performance computing systems.
文摘As a clean and renewable form of energy,photovoltaic(PV)power generation converts solar energy into electrical energy,reducing the consumption of fossil fuels and significantly lowering greenhouse gas emissions.Amidst the global transition towards cleaner forms of energy,countries all around the world are vigorously developing PV technology.
基金supported in part by the Scientific Foundation for Outstanding Young Scientists of Sichuan under Grant No.2021JDJQ0032in part by the National Natural Science Foundation of China under Grant No.52107128in part by the Natural Science Foundation of Sichuan Province under Grant No.2022NSFSC0436.
文摘Traction power systems(TPSs)play a vital role in the operation of electrified railways.The transformation of conventional railway TPSs to novel structures is not only a trend to promote the development of electrified railways toward high-efficiency and resilience but also an inevitable requirement to achieve carbon neutrality target.On the basis of sorting out the power supply structures of conventional AC and DC modes,this paper first reviews the characteristics of the existing TPSs,such as weak power supply flexibility and low-energy efficiency.Furthermore,the power supply structures of various TPSs for future electrified railways are described in detail,which satisfy longer distance,low-carbon,high-efficiency,high-reliability and high-quality power supply requirements.Meanwhile,the application prospects of different traction modes are discussed from both technical and economic aspects.Eventually,this paper introduces the research progress of mixed-system electrified railways and traction power supply technologies without catenary system,speculates on the future development trends and challenges of TPSs and predicts that TPSs will be based on the continuous power supply mode,employing power electronic equipment and intelligent information technology to construct a railway comprehensive energy system with renewable energy.
文摘A BP/CdS heterostructure-based artificial photonic synapse with an ultra-low power consumption is proposed,presenting great potential in high-performance neuromorphic vision systems.
基金financial support from the National Natural Science Foundation of China(Grant No.41827806)the Liaoning Provincial Science and Technology Program of China(Grant No.2022JH2/101300109).
文摘Microwave-assisted mechanical excavation has great application prospects in mines and tunnels,but there are few field experiments on microwave-assisted rock breaking.This paper takes the Sishanling iron mine as the research object and adopts the self-developed high-power microwave-induced fracturing test system for hard rock to conduct field experiments of microwave-induced fracturing of iron ore.The heating and reflection evolution characteristics of ore under different microwave parameters(antenna type,power,and working distance)were studied,and the optimal microwave parameters were obtained.Subsequently,the ore was irradiated with the optimal microwave parameters,and the cracking effect of the ore under the action of the high-power open microwave was analyzed.The results show that the reflection coefficient(standing wave ratio)can be rapidly(<5 s)and automatically adjusted below the preset threshold value(1.6)as microwave irradiation is performed.When using a right-angle horn antenna with a working distance of 5 cm,the effect of automatic reflection adjustment reaches the best among other antenna types and working distances.When the working distance is the same,the average temperature of the irradiation surface and the area of the high-temperature area under the action of the two antennas(right-angled and equal-angled horn antenna)are basically the same and decrease with the increase of working distance.The optimal microwave parameters are:a right-angle horn antenna with a working distance of 5 cm.Subsequently,in further experiments,the optimal parameters were used to irradiate for 20 s and 40 s at a microwave power of 60 kW,respectively.The surface damage extended 38 cm×30 cm and 53 cm×30 cm,respectively,and the damage extended to a depth of about 50 cm.The drilling speed was increased by 56.2%and 66.5%,respectively,compared to the case when microwaves were not used.
基金supported in part by National Key R&D Program of China (2021YFB2500600)CAS Youth multi-discipline project (JCTD-2021-09)Strategic Piority Research Program of Chinese Academy of Sciences (XDA28040100)。
文摘Silicon carbide(SiC) power modules play an essential role in the electric vehicle drive system. To improve their performance, reduce their size, and increase production efficiency, this paper proposes a multiple staked direct bonded copper(DBC) unit based power module packaging method to parallel more chips. This method utilizes mutual inductance cancellation effect to reduce parasitic inductance. Because the conduction area in the new package is doubled, the overall area of power module can be reduced. Entire power module is divided into smaller units to enhance manufacture yield, and improve design freedom. This paper provides a detailed design, analysis and fabrication procedure for the proposed package structure. Additionally, this paper offers several feasible solutions for the connection between power terminals and DBC untis. With the structure, 18dies were paralleled for each phase-leg in a econodual size power module. Both simulation and double pulse test results demonstrate that, compared to conventional layouts, the proposed package method has 74.8% smaller parasitic inductance and 34.9% lower footprint.
