This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is go...This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.展开更多
Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performanc...Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.展开更多
Ultra-thin barrier(UTB) 4-nm-Al Ga N/Ga N normally-off high electron mobility transistors(HEMTs) having a high current gain cut-off frequency( fT) are demonstrated by the stress-engineered compressive Si N trench tech...Ultra-thin barrier(UTB) 4-nm-Al Ga N/Ga N normally-off high electron mobility transistors(HEMTs) having a high current gain cut-off frequency( fT) are demonstrated by the stress-engineered compressive Si N trench technology.The compressive in-situ Si N guarantees the UTB-Al Ga N/Ga N heterostructure can operate a high electron density of1.27×1013 cm-2, a high uniform sheet resistance of 312.8 Ω/, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ Si N in the 600-nm Si N trench, the short-gated(70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode(E-mode). Meanwhile,the novel device also can operate a large current of 610 m A/mm and a high transconductance of 394 m S/mm for the Emode devices. Most of all, a high fT/fmax of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode Al Ga N/Ga N HEMTs. Besides, being together with the 211 GHz/346 GHz of fT/fmax for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of fmax over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E-and D-mode designs the addition of the Si N trench, will promise an enormous competitive advantage in the fabricating costs.展开更多
This paper studies the amplitude of random telegraph noise （RTN） caused by a single trap in the sili- con film of ultra-thin buried oxide （UTBOX） silicon-on-insulator （SOl） devices. The film-defect-related RTN w...This paper studies the amplitude of random telegraph noise （RTN） caused by a single trap in the sili- con film of ultra-thin buried oxide （UTBOX） silicon-on-insulator （SOl） devices. The film-defect-related RTN was identified and analyzed by low frequency noise measurement and time domain measurement. Emphasis is on the relative amplitude AID/ID, which is studied in the function of the front-gate, the back-gate and the drain-to-source biases. Interesting asymmetric or symmetric VDS dependence of switched source and drain are observed and sup- ported by calibrated Sentaurus simulations. It is believed the asymmetry of the VDs dependence of the switched source and drain is related to the lateral trap position along the source and drain.展开更多
文摘This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.
文摘Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.
基金Project supported by the National Key Research and Development Program of China(Grant No.2020YFB1804902)the National Natural Science Foundation of China(Grant No.61904135)+1 种基金the China Postdoctoral Science Foundation(Grant Nos.2018M640957 and BX20200262)the Natural Science Foundation of Shaanxi Province,China(Grant No.2020JQ-316).
文摘Ultra-thin barrier(UTB) 4-nm-Al Ga N/Ga N normally-off high electron mobility transistors(HEMTs) having a high current gain cut-off frequency( fT) are demonstrated by the stress-engineered compressive Si N trench technology.The compressive in-situ Si N guarantees the UTB-Al Ga N/Ga N heterostructure can operate a high electron density of1.27×1013 cm-2, a high uniform sheet resistance of 312.8 Ω/, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ Si N in the 600-nm Si N trench, the short-gated(70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode(E-mode). Meanwhile,the novel device also can operate a large current of 610 m A/mm and a high transconductance of 394 m S/mm for the Emode devices. Most of all, a high fT/fmax of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode Al Ga N/Ga N HEMTs. Besides, being together with the 211 GHz/346 GHz of fT/fmax for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of fmax over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E-and D-mode designs the addition of the Si N trench, will promise an enormous competitive advantage in the fabricating costs.
文摘This paper studies the amplitude of random telegraph noise （RTN） caused by a single trap in the sili- con film of ultra-thin buried oxide （UTBOX） silicon-on-insulator （SOl） devices. The film-defect-related RTN was identified and analyzed by low frequency noise measurement and time domain measurement. Emphasis is on the relative amplitude AID/ID, which is studied in the function of the front-gate, the back-gate and the drain-to-source biases. Interesting asymmetric or symmetric VDS dependence of switched source and drain are observed and sup- ported by calibrated Sentaurus simulations. It is believed the asymmetry of the VDs dependence of the switched source and drain is related to the lateral trap position along the source and drain.
