操作系统是整个计算机系统的核心与基石,其可靠性与安全性至关重要.操作系统的故障或漏洞可能会导致系统崩溃、数据丢失、隐私泄露和安全攻击等问题,特别是在安全攸关系统中,一旦操作系统发生错误,就可能会造成重大人员伤亡或财产损失....操作系统是整个计算机系统的核心与基石,其可靠性与安全性至关重要.操作系统的故障或漏洞可能会导致系统崩溃、数据丢失、隐私泄露和安全攻击等问题,特别是在安全攸关系统中,一旦操作系统发生错误,就可能会造成重大人员伤亡或财产损失.一直以来,如何保障操作系统的安全性和可靠性对学术界和工业界都是一个重大挑战.目前验证操作系统安全性的方法有软件测试、程序静态分析、形式化方法等.其中,形式化方法是最有潜力确保操作系统安全可信的方法,通过使用形式化方法,建立数学模型并进行系统的形式化分析和验证,从而发现潜在的错误和漏洞.在操作系统中,形式化方法可以用于验证操作系统的功能正确性、完整性以及系统安全性等.在已有的针对操作系统形式化验证的成果基础上,提出了一个面向嵌入式操作系统的形式化验证方案,采用VCC(verified C compiler)、CBMC(C bounded model checker)以及PAT(process analysis toolkit)工具分别对操作系统单元层面、模块层面和系统层面进行验证.该方法已成功应用到某操作系统的任务调度架构案例中,对于嵌入式操作系统的分析验证具有一定的通用性。展开更多
A full on-chip CMOS low-dropout（LDO） voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero...A full on-chip CMOS low-dropout（LDO） voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area of the LDO（including the bandgap voltage reference） is 400×270μm^2.Experimental results show that the PSR of the LDO is-58.7 dB at a frequency of 10 Hz and-20 dB at a frequency of 1 MHz.The proposed LDO is capable of sourcing an output current up to 50 mA.展开更多
A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real ...A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.展开更多
文摘操作系统是整个计算机系统的核心与基石,其可靠性与安全性至关重要.操作系统的故障或漏洞可能会导致系统崩溃、数据丢失、隐私泄露和安全攻击等问题,特别是在安全攸关系统中,一旦操作系统发生错误,就可能会造成重大人员伤亡或财产损失.一直以来,如何保障操作系统的安全性和可靠性对学术界和工业界都是一个重大挑战.目前验证操作系统安全性的方法有软件测试、程序静态分析、形式化方法等.其中,形式化方法是最有潜力确保操作系统安全可信的方法,通过使用形式化方法,建立数学模型并进行系统的形式化分析和验证,从而发现潜在的错误和漏洞.在操作系统中,形式化方法可以用于验证操作系统的功能正确性、完整性以及系统安全性等.在已有的针对操作系统形式化验证的成果基础上,提出了一个面向嵌入式操作系统的形式化验证方案,采用VCC(verified C compiler)、CBMC(C bounded model checker)以及PAT(process analysis toolkit)工具分别对操作系统单元层面、模块层面和系统层面进行验证.该方法已成功应用到某操作系统的任务调度架构案例中,对于嵌入式操作系统的分析验证具有一定的通用性。
基金Project supported by the National Science and Technology Major Project,China(No.2009ZX03007-002).
文摘A full on-chip CMOS low-dropout（LDO） voltage regulator with high PSR is presented.Instead of relying on the zero generated by the load capacitor and its equivalent series resistance,the proposed LDO generates a zero by voltage-controlled current sources for stability.The compensating capacitor for the proposed scheme is only 0.18 pF,which is much smaller than the capacitor of the conventional compensation scheme.The full on-chip LDO was fabricated in commercial 0.35μm CMOS technology.The active chip area of the LDO（including the bandgap voltage reference） is 400×270μm^2.Experimental results show that the PSR of the LDO is-58.7 dB at a frequency of 10 Hz and-20 dB at a frequency of 1 MHz.The proposed LDO is capable of sourcing an output current up to 50 mA.
基金supported by State Key Laboratory of ASIC and Systems of Fudan University and NSF(No.61076027)
文摘A stable LDO using VCCS （voltage control current source） is presented. The LDO is designed and implemented on GF 2P4M 0.35μm CMOS technology. Compared with a previous compensation scheme, VCCS can implement a real stable LDO with a small on-chip capacitor of 1 pF, whose stability is not affected by the variable ESR （equivalent series resistance） of the output capacitor. The unit gain frequency of the LDO loop can achieve 1.5 MHz, improving the transient response. The PSR of the LDO is larger than 45 dB within 0-40 kHz. The static current of the LDO at heavy load of 100 mA is 57 μA and the dropout voltage of the LDO is 150 mV. Experimental results show that a setting time of 10 ks is achieved, and the variation of output voltage is smaller than 35 mV for a 100 mA load step in transient response of the LDO.
