A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and...A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and a b uilding block of synthesizing logic.The reference frequency input into this freq uency synthesizer is 25MHz and the synthesized frequency is 1GHz.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
This paper presents a low power, high sensitivity Gaussian frequency shift keying （GFSK） demodu- lator with a flexible frequency offset canceling method for wireless networks for industrial automation process automa...This paper presents a low power, high sensitivity Gaussian frequency shift keying （GFSK） demodu- lator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation （WIA-PA） transceiver fabricated in 0.18 #m CMOS technology. The receiver uses a low-IF （1.5 MHz） architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with 4-180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate （BER）, and consumes no more than 0.26 mA from a 1.8 V power supply.展开更多
文摘A new method of synthesizing 1GHz based on a 0 5μm CMOS D LL is proposed,which can synthesize frequency with simple logic and amplifiers.T he designed frequency synthesizer consists of a DLL (Delay-Locked Loop) and a b uilding block of synthesizing logic.The reference frequency input into this freq uency synthesizer is 25MHz and the synthesized frequency is 1GHz.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low power, high sensitivity Gaussian frequency shift keying （GFSK） demodu- lator with a flexible frequency offset canceling method for wireless networks for industrial automation process automation （WIA-PA） transceiver fabricated in 0.18 #m CMOS technology. The receiver uses a low-IF （1.5 MHz） architecture, and the transmitter uses a sigma delta PLL based modulation with Gaussian low-pass filter for low power consumption. The active area of the demodulator is 0.14 mm2. Measurement results show that the proposed demodulator operates without harmonic distortion, deals with 4-180 kHz frequency offset, needs SNR only 18.5 dB at 0.1% bit-error rate （BER）, and consumes no more than 0.26 mA from a 1.8 V power supply.
