ASIC Design of DA-Based 2-D Inverse Discrete Cosine Transform

Aim To present an ASIC design of DA based 2 D IDCT. Methods\ In the design of 1 D IDCT is utilized a Chen based fast IDCT algorithm, and multiplier accumulators based on distributed algorithm contributes in reducing the hardware amount and in enhancing the speed performance. Results and Conclusion\ VHDL simulation, synthesis and layout design of system are implemented. This 2 D IDCT ASIC design owns best timing performance when compared with other better designs internationally. Results of design prove to be excellent.

SF^2HDL： A Computational Tool of State Transition Diagram Translation

The lack of standard to electronic circuits modeling made possible the development of many tools and modeling languages for electronic circuits. In this way, several tools to be used on different descriptions stage of the designs are necessary. This paper presents a tool called SF^2HDL （Stateflow to Hardware Description Language or State Transition Table） that translates a finite state machine on state transition diagram representation, described by Stateflow tool, into an input file standard for TABELA program or into a file behavioral VHDL （Very High Speed Integrated Circuits Hardware Description Language） directly. The TABELA program was used to optimization this finite state machine. After that, the TAB2VHDL program was used to generate the VHDL code on register transfer level, what permits comparisons with results obtained by synthesis. The finite state machine must be described by Mealy model and the user can describe the machine on high level abstraction using all Simulink supports. The tool was very efficient on computational cost and it made translation of several cases, for the two VHDL description models. Every state machine translated was simulated and implemented on device EP2C20F484C7 using Quartus II environment.

High-Performance FIR Filter Implementation Using Anurupye Vedic Multiplier

In this, today’s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay;area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.

Design and implementation of high-speed real-time data acquisition system based on FPGA

The electromagnetic radiation will result in informa- tion leakage being recovered when computers work. This article presents a high-speed real-time data acquisition system based on peripheral component interconnect （PCI） bus and field programmable gate array （FPGA） for sampling electromagnetic radiation caused by video signal. The hardware design and controlling flow of each module are introduced in detail. The sampling rate can reach 64 Msps and system transfers speed can be up to 128 Mb/s by using time interleaving, which increases the overall sampling speed of a system by operating two data converters in parallel.

Deadlock Detection in FPGA Design: A Practical Approach

Formal verification of VHSIC Hardware Description Language （VHDL） in Field-Programmable Gate Array （FPGA） design has been discussed for many years. In this paper we provide a practical approach to do so. We present a semi-automatic way to verify FPGA VHDL software deadlocks, especially those that reside in automata. A domain is defined to represent the VHDL modules that will be verified; these modules will be transformed into Verilog models and be verified by SMV tools. By analyzing the verification results of SMV, deadlocks can be found; after looking back to the VHDL code, the deadlocking code is located and the problem is solved. VHDL verification is particularly important in safety-critical software. As an example, our solution is applied to a Multifunction Vehicle Bus Controller （MVBC） system for a train. The safety properties were tested well in the development stage, but experienced a breakdown during the long-term software testing stage, which was mainly caused by deadlocks in the VHDL software. In this special case, we managed to locate the VHDL deadlocks and solve the problem by the FPGA deadlock detection approach provided in this paper, which demonstrates that our solution works well.