多分辨率重采样压缩算法硬件系统体系结构研究

主要介绍基于多分辨率重采样算法的图像实时压缩系统体系结构设计。文章首先简要描述多分辨率重采样图像压缩算法 ,然后探讨以硬件系统实现该算法所可能采取的多种不同体系结构。在分析比较各种体系结构特点基础上 ,重点阐述以大规模专用集成电路作为系统核心的体系结构 ;为完成多分辨率重采样图像压缩专用集成电路设计 ,对压缩算法进行了并行化、模块化、层次化处理 ,提出实现多分辨率重采样图像压缩算法的超大规模集成电路结构 ,并且以可编程序门阵列实现。实验结果表明 ,以该结构实现的硬件压缩系统 ,在保证恢复图像质量前提下 ,体积小、质量轻、功耗低、数据处理速度快 ,在原理上 。

Low-complexity systolic architecture for inversion

A modified extended binary Euclid＇ s algorithm which is more regularly iterative for computing an inversion in GF（2^m） is presented. Based on above modified algorithm, a serial-in serial-out architecture is proposed. It has area complexity of O（m）, latency of 5m - 2, and throughput of 1/m. Compared with other serial systolic arehiteetures, the proposed one has the smallest area complexity, shorter latency. It is highly regular, modular, and thus well suited for high-speed VLSI design.