ON THE OPTIMIZATION OF VLSI ALLOCATION IN HIGH-LEVEL SYNTHESIS

Allocation is one of main tasks in the high-level synthesis. It includes module , functional unit allocation, storage allocation and interconnection allocation. This paper models the allocation problem as cluster analysis and applies a new algorithm, neighbor state transition (NST) algorithm, for cluster optimization. It is proved that the algorithm produces an asymptotically global optimal solution with the upper bound on the cost function (1 + O(1/n)2-ε)F*, When F" is the cost of the optimum solution, n is the problem size and e is a positive parameter arbitrarily close to zero. The numerical examples show that the NST algorithm produces better results compared to the other known methods.

A high-level synthesis based dual-module redundancy with multi-residue detection(DMR-MRD)fault-tolerant method for on-board processing satellite communication systems

On board processing(OBP) satellite systems have obtained more and more attentions in recent years because of their high efficiency and performance.However,the OBP transponders are very sensitive to the high energy particles in the space radiation environments.Single event upset(SEU)is one of the major radiation effects,which influences the satellite reliability greatly.Triple modular redundancy(TMR) is a classic and efficient method to mask SEUs.However,TMR uses three identical modules and a comparison logic,the circuit size becomes unacceptable,especially in the resource limited environments such as OBP systems.Considering that,a new SEU-tolerant method based on residue code and high-level synthesis(HLS) is proposed,and the new method is applied to FIR filters,which are typical structures in the OBP systems.The simulation results show that,for an applicable HLS scheduling scheme,area reduction can be reduced by 48.26%compared to TMR,while fault missing rate is 0.15%.

Synthesis of SrTiO_3 for immobilization of simulated HLW by SHS

Strontium titanate synroc samples were synthesized by self-propagating high-temperature synthesis （SHS）. Sr directly took part in the synthesis process. As a result, the loading content issue is basically resolved. The products were characterized by density, microhardness X-ray diffraction, and scanning electron microscopy （SEM/EDS）. The leaching rate was measured by the method of PCT （product consistency test）. The results indicate that the Sr^2＋-SrTiO3 compound is of high density, low leach rate and high stability and the synthesis process is feasible in technology and economy. It can be concluded that the strontium titanate synroc is a perfect material to immobilize HLW.

基于异构平台的卷积神经网络加速系统设计

在计算和存储资源受限的嵌入式设备上部署卷积神经网络,存在执行速度慢、计算效率低、功耗高的问题。提出了一种基于异构平台的新型卷积神经网络加速架构,设计并实现了基于MobileNet的轻量化卷积神经网络加速系统。首先,为降低硬件资源消耗以及数据传输成本,采用动态定点数量化和批标准化融合的设计方法,对网络模型进行了优化,并降低了加速系统的硬件设计复杂度;其次,通过实现卷积分块、并行卷积计算、数据流优化,有效提高了卷积运算效率和系统吞吐率。在PYNQ-Z2平台上的实验结果表明,此加速系统实现的MobileNet网络推理加速方案对单幅图像的识别时间为0.18 s,系统功耗为2.62 W,相较于ARM单核处理器加速效果提升了128倍。

基于Vivado HLS的FPGA开发与应用研究

为在硬件中更快速地实现数字信号处理或图像处理算法,可使用Vivado HLS工具与Zynq系列的全可编程SoC进行FPGA的设计与开发.开发者能够借助它们直接使用C或C++语言进行FPGA的开发,相对于Verilog或VHDL设计而言,开发周期短、成本低。本文详细介绍了Vivado HLS工具的特点与应用等内容,并以"图像色调分离"和"循环编码器"两种不同类型的实例,描述了该工具的使用方法与设计技巧.

基于Vivado HLS的Down Scaler视频系统设计

介绍一种基于FPGA的Down Scaler视频系统设计。系统的核心部件采用Xilinx Kintex-7的板载XC7K325T芯片,系统设计使用Vivado工具,包括使用Vivado HLS进行Down Scaler模块设计。首先按照Vivado HLS的代码规范进行Down Scaler模块的C/C++代码编写,然后利用编译工具生成RTL级代码和综合结果 Down Scaler IP核,最后将Down Scaler IP核与TPG、VDMA等Xilinx视频IP核互连,构建实时视频系统。在满足实时性要求和FPGA资源消耗要求的条件下,该设计实现了对Down Scaler视频算法从PC端软件处理方式向FPGA平台硬件处理方式的移植。

基于Vivado HLS的硬件设计效能评估

本文为了研究面向FPGA芯片的高层次综合工具Vivado HLS在硬件设计中的性能,分别利用C++语言与Verilog语言设计移位寄存器,通过比较两种设计方法在不同输出位宽下,其时序、功耗、PDP以及资源使用量上的差别来评估HLS工具在硬件电路设计上的效率与功能性。实验结果表明,虽然HLS工具综合得到的Verilog代码表现不如手工直接编写的Verilog代码,但其以高级语言作为输入的特性还是能满足让设计师在不需要掌握硬件描述语言的情况下利用FPGA实现算法加速的目的。

METHOD OF HIGH-LEVEL TECHNOLOGY MAPPING BASED ON KNOWLEDGE(RULE)

This paper studies the linkage problem between the result of high-level synthesis and back-end technology, presents a method of high-level technology mapping based on knowl edge, and studies deeply all of its important links such as knowledge representation, knowledge utility and knowledge acquisition. It includes: (1) present a kind of expanded production about knowledge of circuit structure; (2) present a VHDL-based method to acquire knowledge of tech nology mapping; (3) provide solution control strategy and algorithm of knowledge utility; (4)present a half-automatic maintenance method, which can find redundance and contradiction of knowledge base; (5) present a practical method to embed the algorithm into knowledge system to decrease complexity of knowledge base. A system has been developed and linked with three kinds of technologies, so verified the work of this paper.

Register Allocation Algorithm for High-Level Circuit Synthesis for Improved Testability

Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits a higher fault coverage than other algorithms with Tests on some benchmarks show that the algorithm gives less area overhead and even less time delay.

The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT

This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level (RTL) binding and technology mapping subsystem. In more detail, the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.

A Novel Testability-Oriented Data Path Scheduling Scheme in High-Level Synthesis

Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.

A Survey on Performance Optimization of High-Level Synthesis Tools

Field-programmable gate arrays(FPGAs)have recently evolved as a valuable component of the heterogeneous computing.The register transfer level(RTL)design flows demand the designers to be experienced in hardware,resulting in a possible failure of time-to-market.High-level synthesis(HLS)permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions.This provides a promising approach to solve these problems.However,the performance of HLS tools still has limitations.For example,designers remain exposed to various aspects of hardware design,development cycles are still time consuming,and the quality of results(QoR)of HLS tools is far behind that of RTL flows.In this paper,we survey the literature published since 2014 focusing on the performance optimization of HLS tools.Compared with previous work,we extend the scope of the performance of HLS tools,and present a set of three-level evaluation criteria,covering from ease of use of the HLS tools to promotion on specific metrics of QoR.We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR.We find that it needs more efforts on the ease of use for efficient HLS tools.We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process,and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

LP-LDPC:Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis

Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to real-world noises.Fast prototyping field-programmable gate array(FPGA)-based decoder is essential to achieve high decoding performance while accelerating the development process.This paper proposes a three-level parallel architecture,TLP-LDPC,to achieve high throughput by fully exploiting the characteristics of both LDPC and underlying hardware while effectively scaling to large-size FPGA platforms.The three-level parallel architecture contains a low-level decoding unit,a mid-level multi-unit decoding core,and a high-level multi-core decoder.The low-level decoding unit is a basic LDPC computation component that effectively combines the features of the LDPC algorithm and hardware with the specific structure(e.g.,Look-Up-Table,LUT)of the FPGA and eliminates potential data conflicts.The mid-level decoding core integrates the input/output and multiple decoding units in a well-balancing pipelined fashion.The top-level multi-core architecture conveniently makes full use of board-level resources to improve the overall throughput.We develop an LDPC C++code with dedicated pragmas and leverage HLS tools to implement the TLP-LDPC architecture.Experimental results show that TLP-LDPC achieves 9.63 Gbps end-to-end decoding throughput on a Xilinx Alveo U50 platform,3.9x higher than existing HLS-based FPGA implementations.

硬件加速CNN实时图像处理方法

针对CNN算法计算量大、运算耗时长、对PC资源依赖程度高的缺点,提出一种基于Vivado高层次综合硬件加速CNN实时图像处理的方法。将训练好的CNN模型中各参数提取并导入Vivado HLS中,利用C++语言按照Vivado HLS处理规范编写CNN识别算法,实现由FPGA的逻辑资源生成CNN算法对应的RTL级硬件电路,通过Vivado HLS仿真窗口进行CNN识别算法的测试,评估硬件加速CNN算法实时图像处理的效果。实验结果表明,该方法识别MNIST库中10000例手写体样本仅需8.69 s,PC端识别相同样本的时间为30 s,该方法有利于实时图像处理算法向硬件化高性能处理平台ZynqSOC移植。

先心病心音CNN分类算法的硬件加速

为提高先心病心音分类算法的实时性,适用于资源有限的嵌入式设备,提出一种对FPGA进行流水线约束设计的硬件加速方法。将CNN内部计算的并行性与FPGA上的并行硬件对应起来,通过VIVADO高层次综合(HLS)映射CNN算法至FPGA上,在卷积层中的循环上采用流水线约束,子循环会默认展开的方式,提升循环的执行速度。实例仿真计算结果表明,该方法可以很好地利用硬件资源,极大降低计算延时,有效提升算法的实时性。

LDPC译码器中SISO模块的高层次综合实现

日益增长的硬件设计复杂度和越来越短的芯片研发周期给集成电路设计带来了极大的挑战。通过更高抽象层实现硬件设计自动化的方法是解决问题的关键。Vivado TM High-Level Synthesis(HLS)是Xilinx公司发布的高层次综合工具。针对信道编解码LDPC译码器芯片的核心模块—软输入软输出(Soft-Input Soft-Output,SISO)模块,采用HLS设计方法进行了基于C语言模型的实现。HLS的综合结果能与手工使用Verilog实现的性能接近,但明显缩短了设计时间。

High Level Synthesis for Loop-Based BIST

Area and test time are two major overheads encountered duringdata path high level synthesis for BIST. This paper presents an approach to behavioral synthesis for loop-based BIST. By taking into account the requirements of theBIST scheme during behavioral synthesis processes, an area optimal BIST solutioncan be obtained. This approach is based on the use of test resources reusabilitythat results in a fewer number of registers being modified to be test registers. Thisis achieved by incorporating self-testability constraints during register assignmentoperations. Experimental results on benchmarks are presented to demonstrate theeffectiveness of the approach.

Hierarchial Strategy of Testable Design in VLSI System

With the development of VLSI technology, testing design method has been one indispensable fact of the research of VLSI design methodology. Technology of testing design can observably reduce the cost of the chip and help win in time- to-market. Conventional methods of design for test improve the testing performance of the system by modifing the gate-level architecture generally. Re-search in high-level test synthesis has been emphasized on fitting for the trend of high-level VLSI design. In this paper, based on the analysis of different types of testing design methods, a novel compound strategy of design for test in VLSI system is proposed.

FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan

As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.

Fast combination of scheduling chains under resource and time constraints

Scheduling chain combination is the core of chain-based scheduling algorithms, the speed of which determines the overall performance of corresponding scheduling algorithm. However, backtracking is used in general combination algorithms to traverse the whole search space which may introduce redundant operations, so performance of the combination algorithm is generally poor. A fast scheduling chain combination algorithm which avoids redundant operations by skipping “incompatible” steps of scheduling chains and using a stack to remember the scheduling state is presented in this paper to overcome the problem. Experimental results showed that it can improve the performance of scheduling algorithms by up to 15 times. By further omitting unnecessary operations, a fast algorithm of minimum combination length prediction is developed, which can improve the speed by up to 10 times.